Market-leading Hardw are/Softw are Co-Verification Seamless for - - PowerPoint PPT Presentation

Market-leading Hardw are/Softw are Co-Verification

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 2

Seamless for Field Programmable SoC

n FPSoC devices share many of the same challenges of

the SoC and Board methodologies they will replace:

— Hardware & Software - must be developed and verified

together

— Controllability & Observability - gaining access to all

the signal & processor information, pre-silicon & post silicon playback

— Early Availability - designing 1M+ gates is a lengthy

process - how soon can you start software debug?

— System Considerations - most systems will contain

devices (memories, co-processors, etc) outside the FPSoC

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 3

n Seamless Hardware/Software Co-Verification provides a

Virtual Prototyping environment that enables early, productive debug of complex embedded systems

Hardware/Software Co-Verification

CPU Core

Timer & Watchdog

RTOS

Device-1 Driver Device-2 Driver Device-3 Driver

Peripheral

Peripheral

Memory Peripheral

Unique Value-Add Software Unique Value-Add Hardware

n

Early Availability

n

Controllability

— stop clock — single step — “what if?” analysis

n

Observability

— all signals, all

internals available

n

Ease of change

n

Ease of debug

n

Performance profiling

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 4

Virtual Prototyping: Logic Simulation

n

Logic simulation can:

— show how hardware responds to software — model interrupts, resets, other events that

effect software

— show how hardware timing can impact

software execution

— give access and trace of any signal or node

in the design

— allow ‘what if’ analysis of hardware events

n

Simulation can not:

— give visibility of processor or memory internals — show ‘C’ or assembly code — show how software responds to hardware stimuli — simulate sufficient code

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 5

Virtual Prototyping: Software Simulation

n

Software (Instruction Set) Simulation can:

— view code, registers, memory — step through code — show how software reacts to hardware

n

Software Simulation can not:

— model clocks — model external hardware — model interrupts, exceptions, resets — show bus contention, protocol violations,

timing issues

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 6

Virtual Prototyping: Hardware/Software Co-Verification

n

Combining software + hardware simulation gives all the benefits & removes restrictions

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 7

Coherent Memory Server

XRAY Seamless ModelSim

Debug/Flow Control in Co-Verification

n

Controls the flow of data from ISS to Logic Simulator (& back)

n

Without optimizations, all cycles are routed through logic simulator

n

Full debug of all logic & software events

n

Can drive both environments from single location

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 8

Optimizing Co-Verification Performance

n

“Instruction Fetch & Memory Access” Optimization

n

Some or all memory accesses routed direct to memory server

— User specifies which and when

n

Clock cycles driven to logic simulator

Coherent Memory Server

Optimized Fetches, Stores & Loads Non-Optimized Memory Requests

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 9

Optimizing Co-Verification Performance

n

“Time” Optimization

n

Some or all memory accesses routed direct to memory server

— User specifies which and when

n

Clock cycles NOT driven to logic simulator

Coherent Memory Server

Optimized Fetches, Stores & Loads Non-Optimized Memory Requests

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 10

Optimizing Co-Verification Performance

n Optimization Controlling

— Through the Seamless GUI

n switch optimizations on/off n define optimization ‘recipes’

— Through the Logic Simulator

n associate Seamless commands with

hardware events

— Through the Debugger

n associate Seamless commands with

software states or events

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 11

Seamless with Excalibur: Current Status

EBI

SRAM

(Single Port)

SDRAM Controller

DPRAM

SDRAM Interface Flash Interface

Bridge Master Port Slave Port

Dual-Port RAM Interface

ARM922T PLLs

PLD

Stripe

n

Create Seamless Configuration File

— Describe to Seamless

how to invoke the ISS & load the software

— Define the memory

map & configuration

n

Run Co-Verification

— Insert ARM922T PSP — Use Seamless

Compatible Memories

n

Get the Stripe Netlist for Seamless :

EPXAx

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 12

Seamless with Excalibur: Solution

EBI

SRAM

(Single Port)

SDRAM Controller

DPRAM

SDRAM Interface Flash Interface

Bridge Master Port Slave Port

Dual-Port RAM Interface

ARM922T PLLs

PLD

Stripe

n

“Super PSP” Delivery from Mentor Graphics including:

— Excalibur stripe netlist

ready to use with Seamless :

n ARM922T PSP n Seamless-ized

memory models

— Scripts to read

configuration registers to automatically generate Seamless Configuration File

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 13

Seamless ARM922 PSP

VHDL/Verilog Pin Wrapper BUS Interface Model (BIM)

– Peripherals – Bus Cycle Timing – Controllers (DMA, MMU, Cache …)

Instruction Set Simulator (ISS)

– Complete instruction set – Registers – InterruptReset – Instruction Timing Coherent Memory Server

n

ARM922t r0 == ARM920t r1 with 8KB I/D Caches

n

Based on high-performance, cycle accurate co- verification Model from ARM

n

Supports XRAY, ADU and ARMSD debuggers

n

Interface to ModelSIM, and all popular Verilog and VHDL simulators

n

Integrated with 3rd party tools (e.g. Verisity SpecMan Elite)

Seamless

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 14

ARM Cores Support

n Mentor Graphics continues to be the leading

supplier of ARM processor co-verification models

— ARM7™Family — ARM9™Family — ARM9E™Family — ARM10™Family — ARM Jazelle Technology™Family

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 15

Seamless with C-Bridge

n Extend co-verification to reach C-based prototyping and

accelerated verification

— Support for integration of ‘C’ models — Enables rapid prototyping of functionality & performance — Earlier verification at higher abstraction — Single language to refine into either HW or SW

n Provide API to support all popular dialects of C

— Anything that exposes a C interface and whose interface

can be expressed in a dataflow, cycle or event semantics

— Support ANSI C, SystemC and CynLib models

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 16

‘C’ HW .dll

n

Load C HW dynamic library from Seamless configuration file

C C Host Host Code Code Debug Debug

Seamless With C-Bridge

CPU CPU Core Core Memory Memory Mem Mem Cont Cont. . Glue Glue Logic Logic I/O I/O DSP DSP Core Core IP IP CPU CPU Perif Perif. . CPU CPU Perif Perif. . Glue Glue Logic Logic I/O I/O DSP DSP Core Core IP IP CPU CPU Perif Perif. . CPU CPU Perif Perif. .

Coherent Memory Server

n

No changes to HDL or SW code

New HW New HW Abstract ‘C’ Bus Abstract ‘C’ Bus Peripheral Peripheral C-Bridge C-Bridge Bus Access API Bus Access API

n

Use C-Bridge API to interface C model into design

New New HW HW

Pins

n

Optional connection of control pins

HDL Design Application SW

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 17

Seamless Co-Verification Summary

n Virtual Prototyping

— provides a flexible, controllable environment for the

design and debug of complex systems

n Seamless Hardware/Software Co-Verification

— links together hardware and software simulation

environments into an effective Virtual Prototype

n Seamless / Excalibur Integration

— allows Excalibur users to rapidly create Seamless

configuration file and to focus on the validation of their original SW against their original HW

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 18

For More Product Information

n www.mentor.com/seamless n seamless_info@mentor.com n Customers Successes :

www.mentor.com/seamless/cust_successes

— Alcatel : “Altera FPGA Platform Evaluation Using Seamless”

n Seamless Technical Workshops

— Request a workshop in your area

@ www.mentor.com/seamless/workshops/description.html

SB & AD, SoPC Seminars - HW/SW CoVerification, April/May 2002 - Company Confidential 19