Unit 18 Field Programmable Gate Arrays (FPGAs) HARDWARE - PowerPoint PPT Presentation

18.1 18.2 Unit 18 Field Programmable Gate Arrays (FPGAs) HARDWARE IMPLEMENTATION Implementing Logic Functions with Memories TARGETS 18.3 18.4 Processing Logic Approaches Progression of HW Logic Density • Recall HW/SW designs sit on a continuum Application Specific Hardware • Suppose I want to implement: F = (X+Y)*(A+B) (no software) • Our ability to design hardware components with Custom Hardware (Faster, Less Power) • Flexibility, Design Time greater numbers of gates/transistors has Computing System – Logic that directly implements a specific task increased exponentially Performance Continuum – Example above may use separate adders and a Cost • ______ Scale Integrated (____) Circuits multiplier unit • General Purpose (GP) Processor/Microcontroller – 1960’s and 1970’s (Design Time, Cost) – A few gates on a chip (74LS00 has 4 NAND gates) – Logic designed to execute SW instructions • _______ Scale Integrated (____) Circuits – Provides basic processing resources that are reused by Processor – 1970’s each instruction Executing Software – Around a hundred gates per chip (4-bit adder) • What if I want to perform: (X*Y) + (A*B) • _______ Scale Integrated (____) Circuits Data in Mem. – What's easiest to redesign? • ____________Scale Integrated (_____) Circuits CPU control Instruc. X + – 100’s of millions of gates Store Y F (Adder) * ADD T,X,Y + * ADD S,A,B A + MUL F,T,S Proc B (Adder) GP Proc. Implementation Custom HW Implementation of (X+Y)*(A+B)

18.5 18.6 ASICs ASICs • Application Specific Integrated Circuits (ASICs) is another name for a typical "chip" • Computer engineers determine the gates and their interconnection that performs a specific task/application – Start with high level "behavioral" description – Use CAD software tools to refine that to logic gates – Use CAD software tools to refine that to transistors and where each should be located on the surface of the chip and how they should be wired together In an ASIC design, a unique chip will be – From there the chip is fabricated and mass-produced manufactured that implements our design at • Design process is expensive, and once which point the HW design is fixed & cannot fabricated the design cannot be changed (but it be changed (example: is fast and uses less power) Pentium, etc.) 18.7 18.8 Where are FPGAs Used Motivation for Reconfigurable Logic • Could we get some of the benefits of both hardware (speed/power) AND • Datacenters software (flexible/reusable) – Bing search engine • Yes…enter Field Programmable Gate – Real-time data analytics Arrays (FPGAs) – Has prebuilt, generic hardware constructs FPGA’s have “logic – Compression and encryption resources” on them that that can be configured and interconnected we can configure to – High-frequency trading based on one design and then reconfigured implement our specific design. We can then and interconnected later for another design • Robots and Rovers reconfigure it to implement another design • Let's learn more about the secret – JPL and the Mars Rovers ingredient to FPGAs…memories! • Telecom Computing System Continuum Application Microcontroller/Processor Specific Hardware Executing Software • Aerospace (no software / custom chip) Reconfigurable Hardware; FPGAs

18.9 18.10 Dimensions and Operations USING MEMORIES TO BUILD MEMORY BASICS COMBINATIONAL CIRCUITS 18.11 18.12 Memories ROM’s ROM • Memories are just _____ • Memories store (write) and retrieve (read) of data with rows and A 0 0 0 1 1 data 0 A 1 columns 1 0 1 0 1 A 2 – Read-Only Memories (ROM’s): Can only retrieve • When data is read, one 0 1 0 0 2 data (contents are initialized and then cannot be entire ____ of data is read 0 1 1 1 3 changed) out 4 1 1 0 1 5 – Read-Write Memories (RWM’s): Can retrieve data • The row to be read is Address 1 0 0 0 Inputs 6 selected by putting a 0 1 1 0 and change the contents to store new data 7 binary number on the 1 0 1 1 _______ inputs Data D 3 D 2 D 1 D 0 Outputs

18.13 18.14 ROM’s Memory Dimensions ROM ROM • Example • Memories are named by 0 A 0 A 0 – Address = 4 10 = 100 2 is 0 0 1 1 their dimensions: 0 … 1 0 0 0 A 1 A 1 provided as input 1 0 1 0 1 0 1 1 – Rows x Columns 1 A 2 … – ROM outputs data in that 0 1 0 0 0 0 2 A n-1 2 • n rows and m columns => row (1101 bin.) 0 1 1 1 3 __ x ___ ROM . 4 1 1 0 1 . • n rows => log 2 n address bits . Address: 5 1 0 0 0 100 2 = 4 10 …or… 6 2 n -2 0 1 1 0 0 0 2 k rows => k address bits 7 1 0 1 1 1 1 2 n -1 • m cols => m data outputs D 3 D 2 D 1 D 0 D m-1 D 0 Data: Row 4 is 1 1 0 1 output 18.15 18.16 RWM’s RWM’s 8x4 RWM 8x4 RWM • Writable memories • Write example provide a set of data A 0 A 0 1 – Address = 3 10 = 011 2 0 0 1 1 0 0 1 1 0 0 A 1 1 A 1 inputs for write data (as – DI = 12 10 = 1100 2 1 0 1 0 1 0 1 0 1 1 A 2 0 A 2 opposed to the data – R/W = 0 => Write op. 0 1 0 0 0 1 0 0 2 2 Address Address 1 1 0 0 outputs for read data) Inputs Inputs 0 1 1 1 • Data in row 3 is 0 1 1 1 3 3 DI 0 0 DI 0 • A control signal R/W 4 1 1 0 1 overwritten with the new 4 1 1 0 1 DI 1 0 DI 1 (1=READ / 0 = WRITE) is 5 value of 1100 2 . 5 DI 2 1 0 0 0 1 DI 2 1 0 0 0 Data Data provided to tell the DI 3 1 DI 3 6 6 0 1 1 0 0 1 1 0 Inputs Inputs memory what operation 7 7 1 0 1 1 1 0 1 1 R/W R/W 0 the user wants to perform DO 3 DO 2 DO 1 DO 0 R/W Data DO 3 DO 2 DO 1 DO 0 Data ? ? ? ? Outputs Outputs

18.17 18.18 Memories as Look-Up Tables • One major application of memories in digital design is to use them as LUT’s (Look-Up Tables) to implement logic functions – This is the core technology used by FPGAs (Field- Programmable Gate Arrays) • Idea : Use a memory to hold the ____________ of Look-up tables… a function and feed the inputs of the function to USING MEMORIES TO BUILD the __________ inputs to "__________" the COMBINATIONAL FUNCTIONS answer 18.19 18.20 Implementing Functions w/ Memories Implementing Functions w/ Memories 8x1 Memory 8x1 Memory 8x2 Memory 8x2 Memory Z 0 Z 1 A 0 A 0 A 0 A 0 1 1 0 0 0 0 0 0 0 0 X Y Z F X Y Z C S Y A 1 1 A 1 Y A 1 0 A 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 X A 2 1 A 2 X A 2 1 A 2 0 0 1 0 0 0 1 0 1 1 1 0 1 0 1 2 2 2 2 X,Y,Z inputs 0 1 0 1 0 1 0 0 1 “look up” 1 1 1 0 1 0 3 3 3 3 the correct X 0 1 1 1 A 0 0 1 1 1 0 Y A 1 answer 4 0 4 0 4 0 1 4 0 1 D 0 Z F A 2 1 0 0 0 1 0 0 0 1 8x1 Mem. 5 5 5 5 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 6 6 6 6 0 0 1 0 1 0 1 1 0 0 1 1 0 1 0 7 7 7 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X D 0 D 0 D 1 D 0 D 1 D 0 Arbitrary Multi-bit function F Logic Y (One's count) 1+0+1 = 10 Z Function F 0 C S 1 0 Use a memory with the same dimensions as 'output' side of the truth table. Use a memory with the same dimensions as 'output' side of the truth table. It's almost TOO easy. It's almost TOO easy.

18.21 18.22 3-bit Squaring Circuit 4x4 Multiplier Example Determine the dimensions of A0 ROM • Q: What size memory A1 the memory that would be Inputs Outputs would you use to build B=A 2 A2 0 A A 2 A 1 A 0 B 5 B 4 B 3 B 2 B 1 B 0 necessary to implement a our 3-bit squaring 4x4-bit unsigned multiplier A3 2 0 0 0 0 0 0 0 0 0 0 0 with inputs X[3:0] and Y[3:0] A4 circuit? and outputs P[??:0] A5 1 0 0 1 0 0 0 0 0 1 1 • A: ____ memory A6 20 Question: How many bits 2 0 1 0 0 0 0 1 0 0 4 • Q: What would you A7 are needed for P? 3 0 1 1 0 0 1 0 0 1 9 39 connect to the address Question: What are the 4 1 0 0 0 1 0 0 0 0 16 inputs of the memory? contents of the numbered ... 5 1 0 1 0 1 1 0 0 1 25 rows? • A: _______ 6 1 1 0 1 0 0 1 0 0 36 Example: • Q: What bits would you X 3 X 2 X 1 X 0 =0010 7 1 1 1 1 1 0 0 0 1 49 program into row 5 of 255 Y 3 Y 2 Y 1 Y 0 =0001 the memory? P = X * Y = 2 * 1 = 2 • A: _______________ = 00010 P0 18.23 18.24 Implementing Functions w/ Memories • To implement a function w/ n-variables and m outputs • Just place the output truth table values in the memory • Memory will have dimensions: 2 n rows and m columns – Still does not scale terribly well (i.e. n-inputs requires memory w/ 2 n outputs) – But it is easy and since we can change the contents of memories it allows us to create "reconfigurable" logic FPGAS – This idea is at the heart of FPGAs