[PDF] - 0.1 CMS HCAL T rigger and Readout Electronics Pro ject The PDF Document

SLIDE 1 0.1 CMS HCAL T rigger and Readout Electronics Pro ject The

v

erall tec hnical co

rdination

for the HCAL trigger and readout electronics (T ri- D AS) pro ject will b e lo cated in the Maryland HEP group, led b y Drew Baden (WBS Lev el 3 manager). In addition to this pro ject managemen t task, Professor Baden will also b e sup ervising the design

f

the system, and the HCAL T rigger and Readout (HTR) cards. These cards will receiv e the ra w data, main tain the Lev el 1 pip eline, transmit trigger primitiv es to the Lev el 1 system, and transmit Lev el 1 accepted data to a concen trator b

ard

(in the same VME crate) for buering and transmission to Lev el 2 and D A Q. This pro ject is describ ed b elo w. 0.1.1 In tro duction The HCAL upp er lev el readout system is dened as ev erything b et w een the

ptical

b ers carrying the HCAL data from the detector, and the input to the L2/L3 pro cessor F arm. The

v

erall system design and its con text within CMS HCAL and T rigger is sho wn in gure 1. P arameters are as in table 1. The full readout system consists

f

24 VME crates. Eac h crate will b e resp

nsible

for receiving HCAL data, main taining the 40MHz pip eline, main taining sync hronization via the TTC, and preparing and transmitting the data for b

th

Lev el 1 and Lev el 2/D A Q. T

do

this, the HCAL readout crate will con tain:

HTR

{ HCAL Readout and Trigger cards: these cards are the w

rkhorse

for receiving and pro cessing ra w data for the Lev el 1 trigger, as w ell as p erparation for Lev el 1.

DCC

{ Data Concen trator Ccard: this card receiv es Lev el 2 data from eac h HTR card in the crate in preparation for transmission to Lev el 2 and the CMS D A Q net w

rk.
HR

C { HCAL Readout Con trol card: this card is resp

nsible

for fast and slo w monitoring, as w ell as ancillary trigger con trol distribution and whatev er functionalit y is not in the HTR and DDC card. This card will ha v e an

n

b

ard

CPU. Eac h crate will consist

f

18 HTR cards, 1 DCC, and 1 HR C card, and will service a single Device Dep enden t Unit (DDU), moun ted as a PCI mezzanine card (PMC)

n

the DCC, for Lev el 2/D A Q feeding. The

ptical

b ers supplying the readout crates are not included in the system. The trigger links, ho w ev er, are included, and p

ssibly

the HCAL DDU as w ell although this has not b een en tirely settled as

f

this time. Buer sizes and transmission requiremen ts will all b e based around an exp ected a v erage Lev el 1 accept rate (L1A)

f

100kHz. The Lev el 2 accept rate is irrelev an t for these considerations. Crates will reside in a ro

m

near the detector, but b elo w the surface. 0.1.2 Upp er Lev el Readout Crate The readout crate is mec hanically a 9U x 400 mm VME crate. The P3 area is completely user denable, and will b e used b y HTR cards (see section 0.1.3) for transmission

f

trigger primitiv e data to Lev el 1, p

ssibly

via auxiliary bac kplane cards but also p

ssibly

via direct connectors, eliminating an y P3 bac kplane and asso ciated auxiliary cards. The latter approac h is seen as a cost sa vings. W e an ticipate that w e will need the middle ro w

f

P2 1

SLIDE 2

Front End Electronics

D C C H T R H T R

18 HTR Cards

H T R H T R

Level 1 T rigger

Level 1 T rigger Data

Vitesse,Copper Link, 20m cables, 1 Gbps

Level 2/Raw Data 200 Mbps per link

FED H R C

T T C 16 16 16 16

1 Gbps fibers

(2 channels/fiber)

Link to Level 2/DAQ

Figure 1: HCAL Readout and T rigger Crate. (for VME 32) for calibration and monitoring I/O, in v

lving

the particular implemen tation for the VME crate CPU card. HCAL data arriv es at eac h crate via

ptical

b er links whic h deliv ers data at appro x- imately 1 Gbps using the HP G-Links proto col. Eac h b er will deliv er 2

r

3 c hannels w

rth
f

data, to b e determined (it dep ends

n

whether w e run the b ers at 800 Mbps

r

1.6 Gbps). As describ ed ab

v

e, there will b e a total

f

18 HTR cards p er VME crate, and eac h HTR card is an ticipated to service 12

r

16 b er inputs. Once arriv ed, the data is transformed, buered, and pip elined in the HTR card. While in the pip eline, data is prepared (Lev el 1 \trigger primitiv es" are constructed) and transmitted to the Lev el 1 framew

rk
v

er copp er cables. These trigger primitiv e cables will carry appro ximately 2 \trigger to w ers" p er cable, with eac h trigger to w er constituting the signal in b

th

the fron t and bac k section

f

an HCAL ph ysical to w er. This results in 8 cables p er HTR card,

r

144 p er crate. The maxim um a v erage L1 accept rate is required to b e appro ximately 100kHz. If the L1 trigger passes the ev en t, the data stored in the pip eline buers is collected, pro cessed and transmitted to the DCC for concen tration

v

er simple c hannel-link copp er cables,

ne

p er HTR card, where it w aits un til it can b e transferred to the D A Q system via DCC input cards. The DCC will hold appro ximately 1000 ev en ts in its in ternal buers. The HR C card serv es as the in terface in the crates for b

th

slo w and fast monitoring, as w ell as pro viding 2

SLIDE 3 HCAL readout crates 22-30 DCC cards p er crate 1 HR C cards p er crate 1 HTR cards p er crate 18 Input b ers p er HTR 16 (12) HCAL c hannels p er b er 2 (3) HCAL c hannels p er HTR 32 (36) HCAL c hannels p er crate 576 (648) TOT AL HCAL c hannels 13,824 TOT AL HTR cards 463 (413) TOT AL DCC cards 35 (26) T able 1: HCAL upp er lev el readout system parameters. a home for a TTC receiv er (TTCRx). TTC signals will b e deliv ered b y the HR C card to the 18 HTR cards in the crate, insuring sync hronization. 0.1.3 The HTR Card In this section w e discuss the HTR card, whic h consist

f

an input section for ra w data receiving, a Lev el 1 P ath con taining the Lev el 1 preparation and transmission capaibilit y to the Lev el 1 framew

rk,

and a Lev el 2/D A Q P ath consisting

f

the pip eline storage and Lev el 1 accept buering used for transmission to the DCC. The HTR design tak es adv an tage

f

the curren t (and pro jected) a v ailabilit y

f

large aordable FPGA c hips with

10

6 gates and

10

3 I/O pins. This design (as

pp
sed

to ha ving separate cards for the separate receiving and trigger functions) allo ws a merging

f

the readout and trigger prepro cessing functionalit y in to a single card, decreasing the engineering and pro duction costs (few er dieren t cards) and allo wing for few er c hannels p er card (more cards with readout capabilit y). Input Section The HCAL calorimeter signals are digitized at eac h crossing (40 MHz). Eac h HCAL QIE c hannel will pro duce a 7-bit n um b er p er crossing as a measure

f

the energy in the HCAL elemen t. The digital 7-bit v alue is a v arian t

ating

p

in

t format, consisting

f

2 bits

f

scale (exp

nen

t) and 5-bits

f

ADC digitization (man tissa). Since there are 4 capacitors p er QIE

utput,

there will b e an additional 2 \CAP" bits transmitted with the QIE digital n um b er. The CAP bit will b e used to correct for the v ariation in eac h sample- and-hold capacitor. T ransmission will b e via b er

ptics

using the HP G-Links proto col running in enco ded mo de with 20 bit frames. Eac h frame will consist

f

the data from 2 QIE c hannels (2x7=14 bits) plus the 2 CAP bits for a total

f

16 data bits p er frame. The rate

f

transmission will b e at 40 Mframes/sec for an total data transmission bandwidth

f

appro ximately 700Mbit/sec[1 ]. The b ers whic h deliv er data to the HTR cards will plug in to the fron t panel. This sc heme alleviates engineering R&D necessary for successful input

v

er the P3 bac kplane, 3

SLIDE 4 and tak es adv an tage

f

the G-links built-in receiving and deserializing capabilit y . As sho wn in gure 0.1.3, the receiv er section

f

the HTR card will add a \frame bit" whic h will tag transmission errors. Sync hronization errors in the cap bit will b e agged and transmitted during those buc k ets that come in the

rbit

gap, in the form

f

an error co de[1 ]. A PLD will receiv e the 16 bits

f

data along with the frame bit, and transmit sim ultaneously to the Lev el 1 and Lev el 2 paths for pro cessing. Note that the PLD will ha v e the TTC timing information a v ailable. Figure 2 sho ws a sc hematic

v

erview

f

the HTR card.

(366.7mm x 400mm)

VME J1 VIPA J0 VME J2 Point-to-Point Tx to DCC 16 HP G-Links Fiber+Rx chip Level 1 Trigger Primtives Path TTL input fromTTC Level 2 Path with Pipeline and Derandomizer buffers Output to Level 1 Framework

Figure 2: HTR card la y

ut

Lev el 1 P ath The L1 tap needs to b e pro cessed and summed with its

ther

depth segmen ts for that eta-phi to w er b efore b eing sen t to the L1 trigger. The HCAL signals are collected

v

er a p erio d

f

5 crossings. The rst t w

are

for baseline subtraction, the last three are the time it tak es to collect the energy . The tapp ed L1 signals m ust b e pro cessed to giv er the energy in 4

SLIDE 5

HP G-Links: 16 bits data 20 bit frames 40 Mframe/sec

Rx

Level 1 Path Level 2 Path

2 1

PLD

Ch A data Ch B data 7 7 Ch A data 9 1 Frame bit

PLD

Beam Crossing Fiber Input Ch B data 9 Beam Crossing Cap bits

Figure 3: HTR input section. the single b eam crossing whic h created the energy . The MCM con tains a simple pro cessor for this purp

se.

Ho w ev er, w e should dev elop an algorithm for implemen tation in a gate arra y as an alternativ e should w e not use the MCM. The summing is done b y a com bination

f

the readout card and trigger card. F

r

the barrel, there are

nly

t w

depth

segmen ts for eac h to w er. This sum is p erformed

n

the readout card. F

r

the endcap calorimeters there can 2,3

r

4 segmen ts whic h need to b e added. No more then t w

are

done

n

the readout card, further summing is done b y the trigger cards. The forw ard calorimeter is ev en more complex. After summing, the 10 bits with least coun t

f

.5 GeV are pic k ed

ut
f

the 16 and sen t to the adjacen t trigger card b y parallel connection across the fron t panel. The Lev el 1 P ath is fully pip elined with no buering. As sho wn in gure 4, c hannels whic h corresp

nd

to the t w

HCAL

depths in a single HCAL to w er will b e added together in to a 17-bit data w

rd

and passed through a Lev el 1 \lter" whic h will determine what energy to b e asso ciated with what b eam crossing, pro ducing a 16-bit w

rd.

The lter will implemen t a sc heme in v

lving

the energy in v e consecutiv e buc k ets. The most lik ely sc heme will in v

lv

e adding the energy in the 5 to w ers A, B, C, D, and E with the w eigh ts suc h that the

utput

will b e giv en b y Output = 1:0

(A

+ B + C )

1:5
(D

+ E ); th us in tegrating

v

er the three buc k ets whic h had real energy , subtracting an y common baseline. W e plan to implemen t this lter using an FPGA, since these w eigh ts in v

lv

e

nly

factors

f

2. The resultan t 16 bits

f

data is then assigned to a particular crossing (main taining the pip eline). A \m uon bit", the result

f

a windo w calculation for the presence

f

a m uon, is then pro duced and added to the data as a \feature bit". The 16 bit HCAL to w er energy is then sub ject to a truncation and

v

ero w calculation, eliminating 6 bits, and then sen t through a non-linear transformation further reducing the to w er energy to 8 bits. Along with the feature bit, these 9 bits are com bined with 9 bits

f

data from another to w er and merged in to a 24 bit Lev el 1 format for transmission. As detailed in table 2, the 24 bits

f

Lev el 1 data will include 9 bits eac h from 2 to w ers, plus 5 bits

f

Hamming co de for error reco v ery , plus an addition bit signifying the ab

rt

gap. Lev el 2/D A Q P ath 5

SLIDE 6

SUM or Error (FPGA) n(=5?)-bucket memory

24

Level 1 Framework Level 1 "Filter"

Ch1A data Ch1A error 9 1 Ch2A data Ch2A error 9 1 ChA data 17 ChA data 16

Muon Window Overflow & truncation

16 1

Level 1 "Filter"

Ch1B data Ch1B error 9 1 Ch2B data Ch2B error 9 1 ChB data 17 ChB data 16

Muon Window Level 1 Formatter

Feature bit 1 Feature bit

SYNC ASIC SUM or Error (FPGA)

Beam Crossing histogramming to check bunch structure

Non-linear Xform

10 8

Overflow & truncation

16

Non-linear Xform

10 8 8 bits tower1 ET 1 feature bit tower1 8 bits tower2 ET 1 feature bit tower2 5 bits Hamming 1 abort gap flag Beam Crossing

Linearizer Linearizer Linearizer Linearizer

16 16 16 16

Figure 4: HTR Lev el 1 P ath. As men tioned ab

v

e, all data en ters b

th

the Lev el 1 and Lev el 2 /D A Q paths in parallel, and data consists

f

16 bits HCAL energy and 2 bits for cap and frame errors. Figure 5 sho ws a sc hematic

f

the Lev el 2/D A Q path. Data is rst put in to RAM a w aiting a Lev el 1 decision from the Lev el 1 framew

rk.

A deco der will determine from the lev el 1 answ er, b eam coun ter signal, and pip eline dela y whic h data is asso ciated with whic h lev el 1 accept, pro ducing a address p

in

ter to the RAM for the HCAL c hannels. An appropriate set

f

10 data v alues will then b e mo v ed in to a \derandomizing buer" whic h serv es as a v ector buer holding all 10 data v alues and asso ciating these v alues with a particular lev el 1 accept. This buer will ha v e to b e able to hold 10 c hannels

f

18 bits eac h and some n um b er

f

lev el 1 accepts. The arc hitecture

f

the HTR card will ha v e all 32 c hannels' derandomizing buers read

ut
v

er a common in ternal data bus, and passed in to a Lev el 2 lter whic h has the same function as that for Lev el 1, with more precision (hence the need for the additional 5 HCAL c hannels) Lev el 2 lter constructs the appropriate sum, the data is ready for formatting and sending to Lev el 2/D A Q. Eac h

f

these comp

nen

ts are discussed b elo w. 6

SLIDE 7 Purp

se

Bits T

w

er 1 energy 8 T

w

er 1 m uon ag 1 T

w

er 2 energy 8 T

w

er 2 m uon ag 1 Ab

rt

gap ag 1 Hamming bits 5 T

tal

24 T able 2: F

rmat

for the 24 bits

f

Lev el 1 data prepared b y the HTR cards.

RAM

9+1 deRandomizing buffers 9+1 L2 Xmit Control

("SUM"s are calculated here)

Consists of16-bit words:

Header: Event ID (1) Beam crossing/"data state" (1) Data: Data buckets (N 10) SUM from filter (1) Address/error (1)

16

FIFO

16 DCC

Ch data Ch error 9 1

RAM

Ch data Ch error 9 1

N•(9+1 bits)

Level 1 Accepts

32 channels total 9+1

N•(9+1 bits)

L1A decoder

Level 1 Framework L1A

Address pointer

"N" data buckets

12 bits

Beam Crossings 12

Beam Crossing

Linearizer 16+1 Linearizer 16+1

Tx

9+1 12

Figure 5: HTR Lev el 2/D A Q P ath. 0.1.4 Derandomizing Buer 0.1.5 Lev el 2 Filtering As discussed ab

v

e, the Lev el 2 ltering is exp ected to b e more precise than that use for Lev el 1. The lter will use as its input the v alues

f

a single c hannel for some n um b er

f

buc k ets, and com bine them in to an energy and asso ciate that energy with a particular b eam crossing. The lter will ha v e the form: Output = N X i=1 w i D i where N is the n um b er

f

c hannels in v

lv

ed in the sum (e.g. 10), w i corresp

nds

to the w eigh ts and D i corresp

nds

to the 16 bit sum in c hannel i. F

r

instance, for the Lev el 1 lter, N = 5, w 1 = w 2 = w 3 = 1:0 and w 4 = w 5 = 1:5. A Mon te Carlo study will determine the

ptim

um w eigh ts and n um b er

f

c hannels. Note that w e plan to implemen t this lter using the ECAL ASIC. 7

SLIDE 8 0.1.6 Status The curren t eort at Maryland, led b y Professor Baden, is concerned with demonstrating the functionalit y needed b y CMS. Sp ecically , since CMS is a fully pip elined fron t-end trigger and D A Q exp erimen t, it will b e up to the Maryland group to demonstrate that the curren t design will ha v e the capabilit y

f

accepting data at the prescrib ed rate, main taining the pip eline, establishing whic h data from whic h buc k et b elongs to whic h in teraction (at least 98%

f

the data for the HCAl will b e spread

v

er 3 time buc k ets), pro ducing Lev el 1 trigger primitiv es, sending these trigger data to the Lev el 1 trigger framew

rk,

w ait for a Lev el 1 accept

r

reject, and transmitting accepted data to the data concen trator for a D A Q readout cycle. The Maryland group is also c harged with

rganizing

a w

rking

readout system for the Summer 2001 HCAL source calibration pro ject at FNAL. During these tests the HCAL will b e read

ut

at 40MHz for the rst time using the demonstrator system w e are building. A pip eline is not necessary for this test, ho w ev er the fron t-end and D A Q system will b e exercised. A t this time (Spring 2001) w e ha v e pro duced a rst demonstrator protot yp e

f

the HCAL Trigger and Readout (HTR) card (see gure 6). This card will consist

f

8 (out

f

32) input c hannels (2 c hannels p er b er, 2 b ers p er O-to-E con v erter, 2 con v erters) and a large Altera Ap ex 20k400 FPGA. All CMS timing information, whic h comes in

v

er the T rigger Timing Con trol (TTC) system will b e presen t

n

this card, facilitating

ur

learning the CMS TTC system. All rm w are (including VME) will b e written here at Maryland b y T ullio Grassi (lead engineer) and Professor Baden. The HCAL fron t-end will b e em ulated using a Fron t End Em ulator (FEE) b

ard

designed and built at Maryland (see gure 7). This b

ard

pro vides for fak e data (8 b ers, whic h w

uld

driv e 2 demonstrator b

ards),
utput
v

er b er, and all required timing signals. Plans call for the demonstrator system to b e in tegrated b y the summer 2001, after whic h w e will bring a w

rking

system to FNAL for the source tests sometime in late summer. This is a full-time researc h eort, as w e are building a 40MHz pip elined D A Q system from scratc h. W e will b e using a 9U VIP A VME crate, with a P en tium 3 CPU b

ard

running Lin ux (RedHat

r

SUSE) whic h will ha v e VME driv ers. W e are w

rking
n

the hardw are, rm w are for the hardw are FPGAs (b

th

cards), and D A Q system with help from UIC and Princeton. The Data Concen trator Card (DCC) is b eing built b y the Boston Univ ersit y group (Professor James Rolf and Eric Hazen) and this card will b e in tegrated in to the demonstrator system along with all the

ther

cards. By the fall

f

2002, w e will ha v e a full-c hannel pro duction card in progress to meet the

cial

CMS HCAL pro ject milestones. Curren t analysis requires appro ximately 450

f

these cards to b e built and deliv ered to CERN including spares (the n um b er

f

cards can still c hange dep ending

n

some nal design decisions). References [1] Waiting for the FNAL gr

up's

TDR

n

the QIE. 8

SLIDE 9

SLIDE 10