Digital HCAL Electronics Status of Electronics Production Gary - - PowerPoint PPT Presentation

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Digital HCAL Electronics Status of Electronics Production Gary - - PowerPoint PPT Presentation

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Digital HCAL Electronics Status of Electronics Production Gary Drake Argonne National Laboratory CALICE Collaboration Meeting Arlington, TX Mar. 10-12, 2010 RPC DHCAL Collaboration: 36 People, 7 Institutions Argonne National Laboratory

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Digital HCAL Electronics Status of Electronics Production

CALICE Collaboration Meeting Arlington, TX

  • Mar. 10-12, 2010

Gary Drake Argonne National Laboratory

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2

DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Argonne National Laboratory

Carol Adams Mike Anthony Tim Cundiff Eddie Davis Pat De Lurgio Gary Drake Kurt Francis Robert Furst Vic Guarino Bill Haberichter Andrew Kreps Zeljko Matijas José Repond Jim Schlereth Frank Skrzecz (Jacob Smith) (Daniel Trojand) Dave Underwood Ken Wood Lei Xia Allen Zhao

RPC DHCAL Collaboration:  36 People, 7 Institutions

RED = Electronics Contributions GREEN = Mechanical Contributions BLUE = Students BLACK = Physicists

Boston University

John Butler Eric Hazen Shouxiang Wu

Fermilab

Alan Baumbaugh Lou Dal Monte Jim Hoff Scott Holm Ray Yarema

IHEP Beijing

Qingmin Zhang

University of Iowa

Burak Bilki Ed Norbeck David Northacker Yasar Onel

McGill University

François Corriveau Daniel Trojand

UTA

Jacob Smith Jaehoon Yu

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Brief Overview of System

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

General Electronics System Specifications

 Front-end instrumentation to use 64-channel custom ASIC – 1 cm2 pads, 1 meter2 planes, 40 planes,  400,000 channels  Front-end channel consists of amplifier/shaper/discriminator  Single programmable threshold  1 bit dynamic range – Threshold DAC has 8-bit range – Common threshold for all 64 channels per ASIC  2 gain ranges – High gain for GEMs (10 fC - ~200 fC signals) – Low gain for RPCs (100 fC - ~10 pC signals)  100 nSec time resolution  Timestamp each hit – 1 second dynamic range  24 bits @ 100 nSec – Synchronize timestamps over system  Data from FE consists of hit pattern in ASIC + timestamp – 24 bit timestamp + 64 hit bits = 88 bits (+ address, error bits, etc.) – Readout format: 16 bytes per ASIC

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

General Electronics System Specifications (Continued)

 Capability for Self Triggering  Noise, Cosmic rays, Data errors  Capability for External Triggering  Primary method for beam events – 20-stage pipeline  2 Sec latency @ 100 nSec  Capability of FE to source prompt Trigger Bit (simple OR of all disc.)  Capability to store up to 7 triggers in ASIC output buffer (FIFO)  Design for 100 Hz (Ext. Trig) nominal rate  Deadtimeless Readout (within rate limitations)  Zero-suppression implemented in front-end  On-board charge injection with programmable DAC  Design for 10% occupancy  Concatenate data in front-ends  Use serial communication protocols  Slow controls separate from data output stream  Compatibility with CALICE DAQ

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Resistive paint Resistive paint Mylar 1.2mm gas gap Mylar Aluminum foil 1.1mm glass 1.1mm glass Signal pads

HV

Detector Configuration

ASIC Front-End PCB Pad Board Conductive Epoxy Glue Communication Link

8.6 mm

Chamber Construction with Electronics:

Fishing line spacers

Grounding is important…

(Not to Scale)

GND

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

DCAL 64 CH Custom ASIC Data Collector

Front End - On Detector Back End

  • Ext. Clock

(Optional)

DCAL 64 CH Custom ASIC VME Interface

CALICE DAQ

  • Ext. Trigger

Inputs from Detector Pads

Front End Motherboard Data Concentrator

Driver/Receiver Timing Trigger Inputs from Detector Pads Control Data

Control, Timing, Trig Out Data Inputs

Data Collector

VME Timing & Trig Module SLAVE

VME Crate Backplane Driver/Receiver Decoder

Timing & Trig Input Trig Out

4-PR CAT5

VME Timing & Trig Module MASTER To Other SLAVES

System Block Diagram

 Both on Same PCB

24

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

System Physical Implementation

 Plane Construction – A plane consists of 3 independent chambers –  See Lei Xia’s talk Friday

Chambers – 3 per plane Square Meter Plane (3) 32 cm X 96 cm chambers

HV Gas Inlet Gas Outlet

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

System Physical Implementation (Cont.)

Data Concentrator Front End Board with DCAL Chips & Integrated DCON Serial Communication Link

  • 1 per Front-End Bd

Chambers – 3 per plane Square Meter Plane

(2) 32 cm X 48 cm Front End Boards per Chamber

Power

 Front End Board – (24) 64-Ch Chips / Bd – 1536 Channels / Bd

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

System Physical Implementation (Cont.)

 Pad Boards – Glued to Front End Board using Conductive Epoxy – Gluing done by robot, after FEB assembly and check out – More in Lei Xia’s Talk on Friday

Front End Board - Top Pad Board - Bottom

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Data

Power

System Physical Implementation (Cont.)

Data Concentrator Front End Board with DCAL Chips & Integrated DCON Serial Communication Link

  • 1 per Front-End Bd

Chambers – 3 per plane Square Meter Plane

VME Interface Data Collectors – Need 10 Timing Module

  • Double Width
  • - 16 Outputs

Ext. Trig In Optional GPS IN

6U VME Crate

To PC VME Interface Data Collectors – Need 10

6U VME Crate

To PC MASTER TTM SLAVE TTM

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

System Physical Implementation (Cont.)

 Square meter plane mounted on cassette using prototype Front End Boards

Plane #1 !!!

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Some Numbers

 Planes – 38 planes in m3  Detector Granularity – 1 cm2 pads – 10,000 pads/plane – 380,000 ch total  Front End Boards – 6 per plane – 228 total (+ spares)  Chips – 64 ch/chip – 24 chips/FEB – 5472 chips total  Data Collectors – 12 FEB/Data Coll. – 20 Data Coll. total  VME Crates – 2 crates total (1 per side)

 Chip Rates (@ 1 TS/trig) – 1 bit/100 nSec out of chips – 121 bits/TSlice

  • 64 hit bits  8 bytes
  • 24 bits timestamp  3 bytes
  • 3 ctrl bit/byte

– 12.1 uSec/TS/Chip – 24 chips operate in parallel –  82.6 KHz max average event rate – Use Zero Suppression…  DCON Output Rates – 16 bytes/TSlice/chip – 25 nSec/nibble –  12.8 uSec/TSlice/chip – 78 K Tslices/sec max rate – Zero Suppression helps – Example:

  • 4 chips hit/event avg
  • Max event rate: 19KHz

– WC: 78 K / 24 = 3.2 KHz

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Power Distribution System

 Cubic meter detector power requirements: – 3A / FEB @ 5V – 40 planes * 6 FEBs/plane * 3.0 amps/FEB = 720 amps at 5V  Solution: – 5 Wiener PL508 chassis – Each PL508 has six independent 5V at 30 amp supplies – 5 PL508 * 6 PS/PL508 * 30 amps/PS = 900 amps total ampacity – Operate at ~80% of capacity – 1 Wiener supply powers 8 Front End Boards  Power Numbers – 100 mA/ASIC @ 2.5V – 3.9 mW/ch – 3A/FEB @ 5V (ASICs run at 2.5V) – 15W/FEB – 90W/plane – 3.6 KW/cubic meter  Not designed for Low Power…

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Power Distribution System (Cont.)

 Need Power Dist. Box to distribute voltages to Front End Boards  Rack Configuration – Power supplies will fit into one rack  Power Distribution – Custom distribution boxes, with fuses, safe wiring, etc. Wiener PL508 Distribution Box

To 1 Front-End Bd 3A Nominal

30A 30A 30A 30A 30A 30A

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Production Quantities

3 1 2 1 0* 0* Teststands 5 5 3 2 2 20 228 5472 Needed for Detector 8 1 2 Power Dist. Boxes 8 1 2 Wiener Power Supplies 8 2 Timing Module 4 1 VME Processors 5 1 VME Crates 28 3 4 Data Collectors 280 10 42 Front End Bds 8644 2164 1008 DCAL Chips Total Spares Possible Tail Catcher Item

* Use Prototypes

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Status of System Components to Date

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Status of DCAL3 Production

 Chip Fabrication: – 11 wafers, 10,300 chips, fabricated, packaged, in-hand  Chip Testing – All chips tested using robot at Fermilab – Results:

  • 8644 good parts  84% yield  Average
  • 1 bad wafer  25% yield  Did not use

DCAL3 Layout Robotic Chip Tester Chip Storage (~1/2 total)

 Complete

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Status of Front End Board Production

8-layer FE-board (3 layers shown)

 Progress since Lyon – Found 3 problems with prototype FEB

  • LVDS outputs of DCON FPGA not true LVDS  had common mode component
  • We had a single-ended clock line between receiver & FPGA, ~10 cm
  • We found a stability problem with the PLL in the FPGA

– We also found a susceptibility for damage to FEB from Chamber Sparking

  • Fixed using grounding and shielding techniques  System Grounding Plan

 Caused relatively rare errors in data collection - ~1E-8  Required additional iterations in design of prototype to find & fix

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Status of Front End Board Production (Cont.)

 Status today – All problems in layout fixed – All problems in firmware fixed – System has been run in Cosmic Ray Teststand for long periods with no errors – System has been run in “Torture Mode” (self trigger, low threshold) with no errors – System has been operated with a “bad” chamber sparking  Now Robust!

 Production fabrication of PCBs now in progress  FEB Checkout Teststands fully operational

Cosmic Ray Teststand FEB Checkout Teststand (one of two)

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Status of Front End Board Production (Cont.)

 A Few Results

Noise Floor - High Gain Channels

50 100 150 200 250 300 2 4 6 8 1 1 2 1 4 1 6 1 8 2 2 2 2 4 2 6 2 8 3 Threshold DAC Value

Low Gain: ~1.9 fC / THR_DAC_CNT  480 fC Range  Operate ~ 190 fC for RPC High Gain: ~0.3 fC / THR_DAC_CNT  75 fC Range Channel Uniformity for Threshold Scans Using On-board Charge Injection

Entries: 1536 Average: 6.19 RMS: 2.97

Measurements of Noise Floor Single channel measurements, 24 Ch FEB

  • Ext. Trig, No Pad Bd, No Chamber, No HV

Entire Front End Board, 1536 Channels

Factor of 6.4

Noise Floor - Low Gain Channels

100 200 300 400 500 600 700 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Threshold DAC Value

Entries: 1536 Average: 2.04 RMS: 2.41

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Status of Data Collector Production

Courtesy Eric Hazen, BU

 Production – 30 boards fabricated & assembled – Testing ~75% complete – ~15 delivered to Argonne  Will be ready when needed

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Status of Timing & Trigger Module (TTM) Production

Trigger Inputs GPS Receiver Input

 Status – Redesign completed

  • Add outputs: 8  16
  • Makes double-width
  • Add capability to use as

MASTER or SLAVE – Set a bit to select – Production

  • Need 3 for detector
  • Fabrication beginning now
  • Assemble ~ April

 Prototypes OK for now  Will be ready when needed

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Schedule & Plans

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Schedule & Plans

 Projected Production Schedule – ~Produce 1 plane per day, all phases of production

Mar

@ FNAL System Tests Power Dist. Box Power Supplies Timing Module Crates Data Collector Front End Bd DCAL Chips

Dec Nov Oct Sept Aug July Jun May Apr Component

PCB Fab PCB Fab PCB Assembly Checkout Assmbly Checkout Gluing Checkout Assembly Checkout Tests in CRTS Com Data Taking Fab

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DHCAL Electronics – Status & Plans

  • G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington

Summary

 We have completed an extensive development program for the electronics of this project – The design of the Front End Board was by far the most difficult aspect of the project – The prototype system has been thoroughly tested

  • Good electronics noise performance  Careful layout & circuit design
  • Good measurement of cosmic rays
  • Data error rate < 1E-12  through extensive testing

 Production preparations in progress – DCAL ASIC

  • Checkout complete
  • 8600 chips in hand  84% yield

– Front-end Board & Pad Board

  • PCB fabrication in progress
  • Plans & preparations for assembly & checkout in place
  • Still the critical path in the project

– Data Concentrator, Timing Module, Power Dist. Box  Production of all in progress

 Begin tests in Cosmic Ray Teststand in May  Begin installation & commissioning at FNAL in September