USCMS HCAL USCMS HCAL USCMS HCAL TriDAS Update Drew Baden - - PowerPoint PPT Presentation

CMS June 2003

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TriDAS Update

Drew Baden University of Maryland

http://www.physics.umd.edu/hep/HTR/hcal_june_2003.pdf

USCMS HCAL USCMS HCAL USCMS HCAL

CMS June 2003

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HTR Status HTR Status HTR Status

• Rev 1 run Summer 2002 testbeam

Board worked well – all functional requirements met Big concern on mechanical issues for production

• Had a difficult experience with previous board manufacturing
• Rev 2 produced March 2003

Board production changes:

• New assembler, in-house X-ray, DFM review, QC
• Gold plated (Rev 1 was white-tin) for better QC

Changes to HTR:

• Change from Virtex 1000E FBGA (1.00mm) to Virtex2 3000 BGA (1.27mm)
• Added stiffeners
• Moved all SLB/TPG output to front-panel daughterboards
• Modified Rx refclk scheme (the usual TTC/refclk clocking concerns)

Full 48 channel capability (Rev 1 was “half HTR”) As of this date, no issues – this board is functioning well

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Dual-LC O-to-E VME Deserializers

Xilinx XC2V3000-4

Stiffeners 6 SLBs

TTC mezzanine

HTR Rev 3 (cont) HTR Rev 3 (cont) HTR Rev 3 (cont)

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HTR Rev 3 HTR Rev 3 HTR Rev 3

• 30 boards delivered April 21

Checkout consisted of

• All systems except connectivity to SLB
• Fiber links checked out at 1.7Gbaud bit rate (1.6Gbaud is CMS requirement)

Frame clock up to 2.0Gbaud bit rate and it stays synchronized No BER yet…will do a lab measurement soon 12 boards x 16 links ~200 links(~5% of total) with no problems Used both onboard crystal oscillator and external clock for REFCLK

Minor adjustments will be needed for front panels, stiffeners, etc. Will battle test these boards this year

• May synchronous testbeam just completed
• July testbeam
• Vertical Slice tests to commence in the fall

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Clocks and Synchronization Clocks and Synchronization Clocks and Synchronization

• Clocking considerations can be divided into 2

parts:

Deserializers REFCLK: stability critical (80MHz frame rate)

• Stability: must have a very low jitter – 30 to 40ps pkpk spec
• Frequency: TI TLK2501 spec is 100ppm (8kHz) to lock

Measured ~350ppm (30kHz) needed to establish link

LHC variation expected to be few kHz

Once link is established, just needs to be stable (it’s a REFCLK!!!)

• Phase: relationship to LHC clock totally irrelevant

Phase critical clock for pipeline synchronization

• Must be in phase with LHC clock
• Jitter spec is very lose – this clock is used inside FPGA for sequential

logic

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HCAL Clock Fanout HCAL Clock HCAL Clock Fanout Fanout

• HTR clocks provided by a single 9U VME board

Chris Tully/Jeremy Mans from Princeton Has fiber TTC input

• Signals fanned out over Cat6 twisted pair:

TTC stream

• To be used by each HTR and by DCC to decode commands & L1A

BC0

• To be used by SLBs to synchronize TPGs

“40MHz” clock

• To be used by FPGA and SLBs to maintain pipeline

Comes from QPLL

“80MHz” clean clock

• To be used for deserializer REFCLK

Comes from QPLL

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Clock Distribution Clock Distribution Clock Distribution

HTR

TTC fiber TTC CLK80 BC0 CLK40 distribution to 6 SLBs and to 2 Xilinx Brdcst<7:0>, BrcstStr, L1A

O/E

BC0

TTC

TTC

TTC

FPGA .. ..

Test Points for RxCLK and RxBC0

.. .. .. ..

80.18 MHz

.. .. .. ..

TTCrx to Ref_CLK of SERDES (TLK2501) CLK40 CLK80

Princeton Fanout Board

TTCrx QPLL

HTR HTR

Cat6E

• r Cat7

Cable

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TTC receiver - TTCumd TTC receiver TTC receiver -

• TTCumd

TTCumd

• General purpose TTC

receiver board (TTCumd)

TTCrx ASIC and associated PMC connectors

• Will be used to receive

TTC signal by HTR, DCC, and clock fanout boards

• No signal receivers!

Copper/fiber receivers must be on the motherboard Signal driven through TTC connectors

• Tested successfully by

Maryland, Princeton, BU groups

Princeton Fanout Card

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May Testbeam Setup May May Testbeam Testbeam Setup Setup

• Lack of a QPLL or decent equivalent – had to

improvise:

Front-end used commercial Cypress PLL

• Matches GOL 100ps pkpk jitter spec

Fanout card

• No clean 80MHz REFCLK, so provided 2 alternatives:

2xLHC clock from crystal oscillator High quality clock from HP signal and pulse generators Jumper selectable on mezzanine cards

• No clean 40MHz system clock

Just used 40MHz output from TTCrx chip anyway

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May Testbeam Experience May May Testbeam Testbeam Experience Experience

• To establish link:

FE

• TTC 40MHz clock cleaned up by Cypress “roboclock” chip (Cy7B993)
• FE reset signal to GOL

Fanout card

• Fanout from onboard 80.1576MHz crystal oscillator for REFCLK
• Fanout TTC 40MHz clock for system clock

HTR

• TLK2501 link circuitry always enabled

Result: Fiber 1.6GHz link established ok

• No problem locking – worked every time.

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Testbeam Experience (cont) Testbeam Testbeam Experience (cont) Experience (cont)

• Link stability -

VERY PRILIMINARY, STILL STUDYING

Ran 10hr test on 48 fibers

• 3 x 1015 bits
• 20% failed to maintain link
• During synchronized beam running, sent reset between spills to ensure link

Similar tests at Maryland using TI eval board showed no link errors, similar number of bits sent

• Curret plan

Study FE ? HTR link at FNAL this month

• FNAL test stand setup this week

Investigate noise characteristics of H2 environment

• H2 is clearly different than FNAL, Maryland and BU experience

Review of HTR and Fanout card

• Will learn what we need to do from the above
• Best guess

All tests in US indicate solid link, but experience in H2 disagree Probably some kind of new noise component – figure out and correct.

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HCAL TPG HCAL TPG HCAL TPG

• Nothing new since May Electronics Week
• TPG under development…

Preliminary FPGA code for TPGs done

• LUT for linearization (downloadable), 0.5GeV steps, 255Gev max ET
• E to ET and sums over as many as 7 channels

Not implemented in code yet…TBD

• Muon window in E
• BCID filter algorithm TBD from testbeams
• Compression LUTs for output to SLBs

Utilization is ~50% of Virtex2 3000

• We are confident this chip will be sufficient

Simulation effort under way…

• Latency issue

See below – we are working on this…

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HTR TPG Commissioning HTR TPG Commissioning HTR TPG Commissioning

• 2 Xilinx FPGAs per

HTR

3 SLBs per Xilinx Each mounted on triPMC connectors

• Will test internal

connectivity to SLBs at UMD

For signals and for localbus connections

• Need a scheme to test

HTR/RCT connectivity

Not just electrical! Also includes data integrity

SLB SLB SLB SLB SLB SLB

Xilinx Xilinx

R C T

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HTR/RCT Testing HTR/RCT Testing HTR/RCT Testing

• Will build PMC tester card

to mount onto HTR

Host to 1 or more Wisconsin RCT Vitesse receiver boards

• Will run the signals from

this RCT tester card back into Xilinx

Using 1 HTR, both FPGAs –

• ne source, one sink – to test

sending data from HTR to RCT

• Will try to engineer 3-SLB

test to test single Xilinx ? SLB ? RCT

SLB

Xilinx Xilinx

RCT

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HTR Production HTR Production HTR Production

• Full contingent of HTRs: 260 boards

Includes 10% spares, 20% spares for parts

• Full production will begin after:

Testbeam demonstrates I/O works under battle conditions Successful testing of the 6 SLB daughter card functions Understanding of how to meet latency issues

• We are still some clock ticks short, but firmware is still very immature

for the TPG part of the HTR (see slides below)

• Best guess: fall 2003

There is no reason to hurry other than to finish with the R&D part

• f the project

Current board design will be final, perhaps some layout adjustments based on conclusion of testbeam effort

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Overall Commissioning Schedule Overall Commissioning Schedule Overall Commissioning Schedule

• Summer 2003 testbeam

Repeat previous test w/production prototype boards

• Fall 2003 Slice tests

HCAL will join as schedule allows

• 2003/2004 HCAL burn-in

Continue with firmware development/integration as needed

• 2004/2005 Vertical Slice and magnet test

We will be ready All HCAL TriDas production cards involved

• October 05 beneficial occupancy of USC

Installation of all racks, crates, and cards We do not anticipate any hardware integration

• Should be all firmware / timing / troubleshooting

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TPG Latency TPG Latency TPG Latency

“Minimizing the trigger latency”

5-10 HTR TPG path 6 HTR Alignment .5 TOF 50 - 57 TOTAL 4 TPG Cables 3 SLB 2-3 Deserializer 18 Fiber Tx to HTRs 2 GOL 8-9 FE (CCA+QIE) 1 HCAL Optics

Latency Item

• Current total 50 – 57 clocks

Very rough guesses

• Many numbers have not been

measured

• Optimizations:

Fiber cables need to be 90m? HTR firmware needs optimization Deserializer random latency fix TPG cables changed to 15m will save 1 tick Others…main efforts over next 6 months

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TPG Path TPG Path TPG Path

ET

comp

7

10

Muon bit

Sum

Consecutive Time-samples

9

TP

8

QIE-data INPUT LUT

Lineariz. and Et ET[9:0]

2 Compression

LUT

2

Muon LUT

1

Delay to synchronize with BCID

10

L1 Filter

10

Sum

in ET

Peak Detection

TP_Bypass 1

2 2 2

Mask & Reset

“NO-SHOWER” LUT take care of cases where showers can leak into a cell and incorrectly set the muon bit. BCID BCID avoids to flag as a muon the tail of a more energetic event