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Grokking FPGA clock management
Philémon Gardet Jean-François Nguyen <phil@lse.epita.fr> <jf@lse.epita.fr>
Architecture
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Grokking FPGA clock management Philmon Gardet Jean-Franois - - PowerPoint PPT Presentation
Grokking FPGA clock management Philmon Gardet Jean-Franois - - PowerPoint PPT Presentation
Grokking FPGA clock management Philmon Gardet Jean-Franois Nguyen <phil@lse.epita.fr> <jf@lse.epita.fr> Architecture 2 Architecture Overview IO buffers PLLs / DLLs CLBs Interconnect Block RAM 3 CLB
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Architecture Overview
- IO buffers
- PLLs / DLLs
- CLBs
- Interconnect
- Block RAM
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CLB - Configurable Logic Blocks
- Logic Cell:
LUT, carry logic, storage
- Chained carry
- Fast adjacent
interconnect
- clk signal
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PLL & DLL
Input clock Phase-locked loop Delay-locked loop
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Clock Networking
- Fan-out
Clock signal intensity
- Clock skew
Different phases from the same source
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Clock Networking - Clock Tree
- Global networks
Low-skew / High fanout
- Regional networks
Mid-skew / Mid fanout
- Edge networks
Low-skew / high speed / IO
Global Regional
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Clock Tree Strategy
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Timing considerations
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Clock Skew
D Q D Q D Q clk
clk1 clk2 clk3
clk clk1 clk2 clk3
Clock skew
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Short Path
D Q D Q d q1 q2
clk
clk
d q1 q2
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Short Path
D Q D Q d q1 q2 clk clk1 clk2
clk d q1 q2 clk1 clk2
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Short Path - Fixes
- Add delay in data path
- Clock Reversing
- Alternate Phase Clocking
○ DLL ○ Differents edge triggers ○ Clock buffering D Q D Q d q1 q2 clk clk1 clk2
Clock reversing
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D Q D Q d q1 q2 clk1 clk2
Alternate Phase clocking
clk1 clk2
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Place and Route
- Routability
○ Avoid coupling capacitance or detours
- Timing constraints
○ Bound delay on each path
- Power consumption
- Yield
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Timing Analysis
- Minimum clock period is dictated by
the largest delay
- Slack is the tolerated delay before
increasing the minimum clock period
- Critical path has a slack of 0
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Asynchronous &
- thers dumb things
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Metastability
D Q
- Real world
⟶ transitive time
- Intermediate logic state
- Unknown behaviour if output
feeds data to another stage
a c b
a b c
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Combinatory Logic as Trigger - Short paths
- Without any synchronization
no hypothesis about order
- Metastability possibility
a b c d q
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Latches - Race condition
- Asynchronous control
- Transitive state
- Loop ⟶ No idea about
current state
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D Q E a
Combinatory
logic
Combinatory
logic
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Combinatory Logic - Delay blocks
a b c d q
delay delay delay delay
- Force delay on each input
- Control transitive state
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Handshaking pipeline
Sender Receiver Req Ack Data path
delay
Delay to send req signal = worst data setting time
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Asynchronous data encoding protocols - dual rail
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Sender Receiver
Ack
r0 d0 r1 d1
Double the data bus → Assure validity d r value 0 0 Null 1 0 1 0 1 0 1 1 Invalid
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Manual Place & Route
- No depend to place & route
algorithms changes
- Control clock skew and
delays
- Automatization optimized for
asynchronous logic ?
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Thank you!
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Bibliography
- FPGA Architecture, timing, software / Mose Wahlstrom - Lattice R&D Team,
2013
- The real hardware / V. Angeloc - VHDL-FPGA@PI, 2013
- 7 Series FPGAs Clocking Resources User Guide / Lattice, 2017
- iCE40 LP/HX Family Data Sheet / Lattice, 2017
- Routing Algorithms and Architectures for Field-Programmable Gate arrays /
Stephen Dean Brown, 1992
- Design Guidelines for Optimal Results in High-Density FPGAs / Altera, 2003
- Rapid System Prototyping with FPGAs / R.C. Coffer, Ben Harding - Elsevier,
2005
- Application of Specific Delay Window Routing for Timing Optimization in FPGA
Designs / Evan Wegley, Qinhai Zhag - Lattice, 2015
- Clock Skew and Short Paths Timing / Microsemi, 2011
- The Art of hardware architecture / Mohit Arora - Springer, 2012