DSN02 Block Diagram. Use CORDIC IP Core. Counter limit n step - - PowerPoint PPT Presentation

DSN02

• Block Diagram.
• Use CORDIC IP Core.

CORDIC Addr COS SIN clock reset enable Counter limit n step wrap clock reset enable 1 Counter limit n step wrap clock reset enable Counter limit n step wrap clock reset enable 2N

Example

• CReSIS UWB Depth Sounder
• Programmable bandwidth: 150 to 600 MHz.
• 1.6-GSPS, 12-Bit Digitizer.
• 24
• Data

Independent

Rate

Channels.

• Maximum
• 24*1.6e9*12/8 = 57.6 GB/sec
• Typically 8 hour flight
• 8*3600 = 28800 sec
• ~1.6 PB per flight
• 6 weeks in the field (30 flight
• ~50 PB of data

day)

• Need to rely on on-board processing

in real-time to reduce the data rate level. to a manageable

Example: Wideband Operation

Flow Diagram

ADC I/F 1.6 GSPS

Example: Narrow band operation

Flow Diagram

ADC I/F 1.6 GSPS 180-200 MHz I/Q Down Conversion Band Select

decimate

Example Flow Diagram

ADC I/F 1.6 GSPS 180-200 MHz I/Q Down Conversion ?

Filter to Reduce noise decimate

Example Flow Diagram

ADC I/F 1.6 GSPS 180-200 MHz I/Q Down Conversion BPF 180-200 MHz Band Select Band Select

decimate

Example

Flow Diagram

ADC I/F 1.6 GSPS 180-200 MHz I/Q Down Conversion ADC I/F 1.6 GSPS ... I/Q Down Conversion

decimate decimate

BPF 180-200 MHz Band Select

can we make it more robust.

Example Flow Diagram

ADC I/F 1.6 GSPS 180-200 MHz ADC I/F 1.6 GSPS ... I/Q Down Conversion I/Q Down Conversion BPF 180-200 MHz ? Band Select

Example Flow Diagram

ADC I/F 1.6 GSPS 180-200 MHz ADC I/F 1.6 GSPS ... I/Q Down Conversion I/Q Down Conversion BPF 180-200 MHz LPF 800 MHz Band Select

Example Flow Diagram

ADC I/F 1.6 GSPS 180-200 MHz ADC I/F 1.6 GSPS ... I/Q Down Conversion I/Q Down Conversion LPF # of Taps? # of filts BPF 180-200 MHz LPF 800 MHz Band Select Band Select

Example Flow Diagram

ADC I/F 1.6 GSPS ... I/Q Down Conversion LPF # of Taps? # of filts LPF 800 MHz

R R R

Digital Down Conversion

• IF Sampling and faster GSPS ADCs

enable fewer analog components and earlier

• reduced

in the receiver chain. hardware noise and lower complexity.

• Digital

commonly baseband Down used Converters (DDC) are to mix the signal to for subsequent processing. allow the received signal to be converted into the digital domain

• Puts an addition burden on the

digital processor (in real time).

Digital Down Conversion

• Components
• NCO to generate I and Q signals for

quadrature

• Quadrature

mixer. mixer (multipliers).

• y(n) = x(n)*cos(ωn) + j*x(n)*sin(ωn)
• Since it is in the digital domain, don’t

gain need to worry about I & Q phase and

• ffsets.
• What
• But

did we do to the data rate? what good is this?

NCO DDS

Digital Down Conversion

• D
• Data rate reduction
• 1600/(2*20) reduced by a factor of 40.
• 57.6 GB/sec to ~1 GB/sec.
• Need a very good FIR to avoid aliasing
• f out-of-band noise (both

back into the analog and due to the digitizer) pass-band prior to decimation.

ecimate from 1.6 GSPS to 20 MSPS

• Need to store complex values.

Digital Down Conversion

• With a LPF

NCO DDS z-1 b1 b2 z-1 b1 b2 z-1 z-1 z-1 b1 b2 z-1 b1 b2 z-1 z-1

DC Offset can cause problems.

Decimation and Interpolation

• Decimation: Take every Nth sample.

module decimate_3 ( input wire clock, input wire reset, input wire enable, input wire [15:0] in,

• utput reg

[15:0] out,

• utput wire next);

counter ( ... .step(1), .limit(3), .wrap(next)); always@(posedge clock) begin if (reset) out <= 0; else if (enable & next) out <= in; end endmodule

Care must be taken to precondition the signal to avoid aliasing noise or other interference. Usually some type of Nyquist band filtering is applied prior to decimation. Wire “next” is exported from the module to be used as an enable for downstream

• perations.

R

Integrator Filter

• Sample Domain Equation
• 1st order IIR filter with a0 = 1;

y[n] = x[n] + y[n-1]

• Z domain

H(z) = 1/(1-z-1)

• Pole at z = 1 (Critically Stable)

z-1

Comb Filter

• Sample Domain Equation
• Nth order FIR filter with b0=1 ,bN=-1.
• All other terms are 0.

y[n] = x[n] - y[n-N]

• Z-domain

H(z) = (1-z-N)

• N zeros equally spaced around the unit

circle starting at z = 1.

z-N

N=8

Cascade Integrator Comb (CIC)

• The pole at z=1 and a pole at z=0

will be canceled.

• All poles are now at zero, which is

effectively a 7th order FIR filter.

• We have seen this pole zero diagram

before?

z-N z-1

CIC N=8

• h = [1 1 1 1 1 1 1 1];
• sum of 8 values

z-N z-1

As long as the integrator has enough bits to accommodate the

• utput it is ok if it
• verflows.

CIC N=255

• sum of 256 values

z-N z-1

As long as the integrator has enough bits to accommodate the

• utput it is ok if it
• verflows.

z-N uses 255xWidth registers

Cascade Integrator Comb (CIC)

• Now we can decimate.
• If R is an integer factor of N.

z-N z-1 R

Cascade Integrator Comb (CIC)

• Now we can decimate.
• If R is an integer factor of N.
• Running average of N values.

z-N/R z-1 R >>>3

Cascade Integrator Comb (CIC)

• Now we can decimate.
• If R is an integer factor of N.
• Running average of N values.
• Mean Removal

z-N/R z-1 R >>>k

N=2k

muliple rate reduction filters

• What does the net frequency response
• f multiple rate reduction filters?
• Rather than using decimation, just

use enables.

• The result will hold the values for

the decimation value

• Consider a simple fir filter

b = 2 3 2

• Cascade two and decimate in between

by a factor of 2.

2 FIR FIR

muliple rate reduction filters

b1 = [2 3 2] b2_eff = [2 2 3 3 2 2] b1&2_eff = b1 * b2_eff b1&2_eff = [4 10 16 19 19 16 10 4] b3_eff = [2 2 2 2 3 3 3 3 2 2 2 2] b1&2&3_eff = 19 effective terms but we only used 9. Effective number of taps for M-cascaded N-tap filters each followed by a decimation by R.

AD6676: IF Wideband Rec. Subsys. 2.0 to 3.2 GSPS ADC

AD6676