CDA 4253/CIS 6930 FPGA System Design Sequential Circuit Building - PowerPoint PPT Presentation

Processes Modeling Sequential Circuits – Code Template process process (clk) begin begin if if rising_edge rising_edge (clk) then then if reset=‘1’ then if then -- reset logic for memory else else -- functional logic defined -- with sequential statements end if; end if end if ; end process ; end process This template is for synthesizable synchronous designs 36

D Flip-Flop: Edge Triggered Truth table Graphical symbol Q( t +1) Clk D Q Q D D ­ 0 0 ­ 1 1 Cloc ock k 0 – Q( t ) 1 – Q( t ) Timing diagram t t t t 1 2 3 4 Clock D Q Time 37

D Flip-Flop: Edge Triggered -- library not shown entity entity dff is is Q Q D D port ( D, Clock : in port in STD_LOGIC ; Q : out out STD_LOGIC) ; Cloc ock k end entity end entity dff; architecture behavioral of architecture of dff is is begin begin process ( Clock Clock ) process begin begin if rising_edge rising_edge(Clock) (Clock) then if then Q <= D ; end if end if ; end process end process ; end architecture end architecture behavioral; 38

D Flip-Flop: Edge Triggered -- library not shown entity entity dff is is Q Q D D port ( D, Clock port : in in STD_LOGIC; Q : out out STD_LOGIC); Cloc ock k end entity end entity dff; architecture behavioral of architecture of dff is is begin begin process ( Clock Clock ) process begin begin if Clock’event Clock’event and Clock=‘1’ and Clock=‘1’ then if then Q <= D ; end if end if ; end process end process ; end architecture end architecture behavioral; 39

D Flip-Flop: Edge Triggered -- library not shown entity entity dff is is port port ( D, Clock : in in STD_LOGIC ; Q Q D D Q : out out STD_LOGIC) ; end entity dff; end entity Cloc ock k architecture behavioral of architecture of dff is is begin begin process ( Clock Clock ) process begin begin if falling_edge falling_edge(Clock) (Clock) then if then Q <= D ; end if end if ; end process end process ; end architecture end architecture behavioral; To be synthesizable, each process is sensitive on a single clock edge 40

D Flip-Flop: Not Allowed! -- library not shown entity entity dff is is port port ( D, Clock : in in STD_LOGIC ; Q Q D D Q : out out STD_LOGIC) ; end entity dff; end entity Cloc ock k architecture behavioral of architecture of dff is is begin begin process ( Clock process Clock ) begin begin if if rising_edge rising_edge(Clock) (Clock) then then Q <= D ; elsif falling_edge elsif falling_edge(Clock) (Clock) then then Q <= not D ; end if end if ; end process end process ; end architecture behavioral; end architecture 41

D FF with Asynchronous Reset -- library not shown entity dff is entity is port ( D, clock port : in in STD_LOGIC ; resetn : in std_logic; Q : out out STD_LOGIC); end entity dff; end entity architecture architecture behavioral of of dff is is Q Q D D begin begin Cloc ock k process (resetn, clock clock ) process Resetn Re begin begin if resetn resetn = ‘0’ = ‘0’ then if then Q <= ‘0’; elsif elsif rising_edge rising_edge( clock) then then Q <= D ; end if end if ; end process ; end process end architecture behavioral; end architecture 42

D FF with Synchronous Reset -- library not shown entity entity dff is is port port ( D, clock : in in STD_LOGIC; resetn : in std_logic; Q Q D D Q : out out STD_LOGIC); Cloc ock k end entity end entity dff; Resetn Re architecture behavioral of architecture of dff is is begin begin process ( clock clock ) process begin begin if if rising_edge rising_edge( clock) then then if resetn resetn = ‘0’ = ‘0’ then if then Q <= ‘0’; else else Q <= D; end if ; end if end process ; end process end behavioral; end 43

8-Bit Register --Library not shown ENTITY reg8 IS PORT ( D : in in STD_LOGIC_VECTOR(7 DOWNTO 0) STD_LOGIC_VECTOR(7 DOWNTO 0) ; resetn, clock : in in STD_LOGIC ; Q : out out STD_LOGIC_VECTOR(7 DOWNTO 0 STD_LOGIC_VECTOR(7 DOWNTO 0) ); END reg8 ; ARCHITECTURE behavioral OF reg8 IS BEGIN PROCESS (resetn, clock) 8 8 Resetn BEGIN D Q IF resetn = '0' THEN Q <= "00000000” Q <= "00000000” ; ELSIF rising_edge(clock) THEN Clock Q <= D ; reg8 END IF ; END PROCESS ; END behavioral ;` 44

Generic N -bit Register --library not shown ENTITY regn IS GENERIC (N : INTEGER := 16) ; GENERIC (N : INTEGER := 16) PORT( D : in in STD_LOGIC_VECTOR( N-1 downto downto 0); Resetn, Clock : in in STD_LOGIC; Q : out out STD_LOGIC_VECTOR( N-1 downto downto 0 )); END regn ; ARCHITECTURE behavioral OF regn IS BEGIN PROCESS (Resetn, Clock) N N BEGIN Resetn IF Resetn = '0' THEN D Q Q <= ( others others => '0’); ELSIF rising_edge(Clock) THEN Q <= D ; Clock END IF ; regn END PROCESS; END behavioral; 45

Use of Keyword OTHERS others stands for any index value that has not been previously referenced to. Q <= � 00000001 � can be written as Q <= (0 => � 1’, others => � 0 � ) Q <= � 10000001 � can be written as Q <= (7 => � 1 � , 0 => � 1 � , others => � 0 � ) or Q <= (7 | 0 => � 1 � , others => � 0 � ) Q <= � 00011110 � can be written as Q <= (4 downto 1 => � 1 � , others => � 0 � ) 46

Example x <= “0000_0001_0000_0001” other way to write the bit string? 47

N-bit Register with Enable -- library not shown ENTITY regne IS GENERIC (N : INTEGER := 8); PORT ( Enable Enable , Clock : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)); END regne ; ARCHITECTURE behavioral OF regne IS BEGIN N N PROCESS (Clock) Enable BEGIN Q D IF rising_edge(Clock) THEN IF IF Enable = '1' Enable = '1' THEN THEN Q <= D; Clock END IF; regn END IF; END PROCESS; END behavioral; 48

FF Coding Guidelines (Xilinx) ➜ Do not set or reset FFs asynchronously ➜ Such FFs not supported, or ➜ Requiring additional resources -> hurts performance ➜ Do not describe Flip-Flops with both a set and a reset ➜ No FFs with both set and reset ➜ Always describe enable , set , or reset control inputs of Flip-Flop primitives as active-High ➜ additional inverter may hurt performance ➜ See XST user guide for more information 49

Shift Registers 50

Shift Register – Internal Structure Q(1) Q(0) Q(2) Q(3) Sin D Q D Q D Q D Q Clock Enable ENTITY sr4 IS PORT (Enable: IN STD_LOGIC; Sin : IN STD_LOGIC; Clock : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END sr4; 51

Shift Register – Model ARCHITECTURE behavioral OF sr4 IS downto 0); signal signal reg: STD_LOGIC_VECTOR(3 downto BEGIN PROCESS (Clock) BEGIN IF rising_edge(Clock) THEN IF Enable = � 1 � THEN -- shift right reg <= reg (3 (3 downto downto 1) & sin; 1) & sin; END IF; END IF ; END PROCESS ; -- output logic Q <= reg; END behavioral; 52

Shift Register With Parallel Load Load D(3) D(1) D(0) D(2) Sin D Q D Q D Q D Q Clock Enable Q(3) Q(2) Q(1) Q(0) 53

4-bit Shift Register with Parallel Load ENTITY sr4_pl IS PORT (D : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Enable: IN STD_LOGIC; Load : IN STD_LOGIC; Sin : IN STD_LOGIC; Clock : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END sr4_pl; 4 4 Enable D Q Load Sin Clock 54

4-bit Shift Register with Parallel Load ARCHITECTURE behavioral OF sr4_pl IS SIGNAL reg : STD_LOGIC_VECTOR(3 DOWNTO 0); 4 4 Enable BEGIN D Q PROCESS (Clock) Load BEGIN IF rising_edge(Clock) THEN Sin IF Enable = � 1 � THEN Clock IF Load = '1' THEN reg <= D; -- parallel load ELSE 1) & sin; -- shift right reg reg <= <= reg reg(3 (3 downto downto 1) & sin; END IF; END IF; END IF ; END PROCESS; Q <= reg; -- output logic END behavioral; 55

N -bit Shift Register with Parallel Load ENTITY srn_pl IS GENERIC ( N : INTEGER := 8); GENERIC ( N : INTEGER := 8); PORT(D : IN STD_LOGIC_VECTOR( N-1 DOWNTO 0); Enable : IN STD_LOGIC ; Load : IN STD_LOGIC ; Sin : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : OUT OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)); END srn_pl ; N N Enable D Q Load Sin Clock 56

N -bit Shift Register with Parallel Load ARCHITECTURE behavioral OF shiftn IS downto 0); signal signal reg: STD_LOGIC_VECTOR(N-1 downto BEGIN PROCESS (Clock) N N Enable BEGIN D Q IF rising_edge(Clock) THEN Load IF Enable = � 1 � THEN Sin IF Load = '1' THEN reg <= D ; Clock ELSE reg <= reg (N (N-1 1 downto downto 1) & sin; 1) & sin; END IF ; END IF; END IF ; END PROCESS ; Q <= reg; END behavioral; 57

Counters 58

2-bit Counter with Synchronous Reset architecture behavioral of architecture of upcount is is SIGNAL Count : SIGNAL Count : std_logic_vector std_logic_vector(1 DOWNTO 0); (1 DOWNTO 0); begin begin process (Clock) process begin begin if if rising_edge(Clock) then then IF IF Clear = ' = ' 1' THEN THEN Count <= " <= " 00 ”; ”; 2 Clear ELSE ELSE Q Count <= <= Count + + 1 ; upcount END IF ; end if end if ; Clock end process end process ; Q <= Count; Q <= Count; -- output internal state end behavioral; end 59

Counter with Asynchronous Reset ARCHITECTURE behavioral OF upcount _ar IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PROCESS (Clock, Resetn) BEGIN IF IF Resetn Resetn = '0' THEN = '0' THEN Count <= "0000”; Count <= "0000”; ELSIF rising_edge(Clock) THEN IF Enable = '1' THEN IF Enable = '1' THEN Enable 4 Count <= Count + 1 ; Count <= Count + 1 ; Q END IF ; END IF Clock upcount END IF ; Resetn END PROCESS ; Q <= Count; Q <= Count; END behavioral ; 60

N-bit Generic Counter: Exercise ➜ Modify the model below to make it generic LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE USE ieee.std_logic_unsigned.all ieee.std_logic_unsigned.all ; ENTITY upcount_ar IS PORT (Clock, Resetn Resetn , Enable Enable : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ; END upcount_ar ; 61

N-bit Generic Counter: Exercise ARCHITECTURE behavioral OF upcount _ar IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PROCESS (Clock, Resetn) BEGIN IF IF Resetn Resetn = '0' THEN = '0' THEN Count <= "0000”; Count <= "0000”; ELSIF rising_edge(Clock) THEN IF Enable = '1' THEN IF Enable = '1' THEN Count <= Count + 1 ; Count <= Count + 1 ; END IF END IF ; END IF ; END PROCESS ; Q <= Count; Q <= Count; END behavioral ; 62

A Timer that Outputs a Tick per Second 63

A Timer that Outputs a Tick per Second LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE USE ieee.numeric_std.all ieee.numeric_std.all ; ENTITY timer_1s IS PORT( Clock, Resetn Resetn : IN STD_LOGIC_VECTOR(26 DOWNTO 0); tick : OUT STD_LOGIC ) ; END timer_1s; 64

A Timer that Outputs a Tick per Second ARCHITECTURE behavioral OF timer_1s IS SIGNAL Count : unsigned(26 DOWNTO 0); SIGNAL Count : unsigned(26 DOWNTO 0); BEGIN PROCESS (Clock, Resetn) BEGIN IF IF Resetn Resetn = '0' THEN = '0' THEN Count <= (others => ‘0’); Count <= (others => ‘0’); ELSIF rising_edge(Clock) THEN if Count = 100000000 100000000 then Count <= 0; else Count <= Count + 1 ; Count <= Count + 1 ; END IF ; END PROCESS ; tick <= tick <= ‘1’ when Count = ‘1’ when Count = 100000000 100000000 else else ‘0’; ‘0’; END behavioral ; 65

Mod-m Counter Counts from 0 to m-1 , and wraps around LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE USE ieee.numeric_std.all ieee.numeric_std.all ; ENTITY mod_m_counter IS generic( N : integer : 4; –- number of bits M : integer : 10 –- mod-M ); PORT( Reset : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); Clock, Reset q : out std_logic_vector(N-1 downto 0); tick : OUT STD_LOGIC ) ; END mod_m_counter; 66

Mod-m ARCHITECTURE arch OF mod_m_counter IS SIGNAL reg : unsigned(N-1 downto 0); Counter BEGIN PROCESS (Clock, Reset) BEGIN IF Reset = '0' THEN reg <= (others => ‘0’); ELSIF rising_edge(Clock) THEN if (reg = M-1) then reg <= (others => ‘0’); reg <= (reg + 1) mod M; else reg <= reg+1; end if; END IF ; END PROCESS ; q <= std_logic_vector(reg); tick <= ‘1’ when reg = M-1 else ‘0’; END arch; 67

Another Timer Design ➜ User sets a time in seconds ➜ Outputs a tick when time is expired 68

Mixing Description Styles Inside of an Architecture 69

VHDL Description Styles VHDL Description Styles structural dataflow behavioral Components and Concurrent Sequential statements interconnects statements • Registers • Shift registers • Counters synthesizable • State machines 70

Mixed Style Modeling architecture ARCHITECTURE_NAME of architecture of ENTITY_NAME is is -- Declarations: signals, constants, functions, -- procedures, component declarations, ... begin begin -- Concurrent statements: -- Concurrent simple signal assignment -- Conditional signal assignment -- Selected signal assignment Concurrent Statements -- Component instantiation statements -- Process statement -- inside process you can use -- inside process you can use -- -- only sequential statements only sequential statements end end ARCHITECTURE_NAME; 71

PRNG Example (1) ENTITY PRNG IS PORT( Coeff : in std_logic_vector(4 downto 0); Load_Coeff : in std_logic; Seed : in std_logic_vector(4 downto 0); Init_Run : in std_logic; Clk : in std_logic; Current_State : out std_logic_vector(4 downto 0)); END PRNG; ARCHITECTURE mixed OF PRNG is signal Ands : std_logic_vector(4 downto 0); signal Sin : std_logic; signal Coeff_Q : std_logic_vector(4 downto 0); signal Sr5_Q : std_logic_vector(4 downto 0); -- continue on the next slide 72

PRNG Example (2) BEGIN -- Data Flow Sin <= Ands(0) XOR Ands(1) XOR Ands(2) XOR Ands(3) XOR Ands(4); Current_State <= sr4_Q; Ands <= Coeff_Q AND Sr5_Q; -- Behavioral Coeff_Reg: PROCESS(Clk) BEGIN IF rising_edge(Clk) THEN IF Load_Coeff = '1' THEN Coeff_Q <= Coeff; END IF; END IF; END PROCESS; -- Structural Sr4_pl_0 : ENTITY work.Sr4(behavioral) generic map(N => 5); PORT MAP (D => Seed, Load => Init_Run, Sin => Sin, Clock => Clk, Q => Sr5_Q); END mixed; 73

Sequential Logic Modeling

Sequential Logic – Overview reg_next inputs register reg clk output 75

Sequential Logic – VHDL Style 1 architecture arch of architecture arch of seq_template is is signal signal reg : std_logic_vector(N-1 downto downto 0); begin begin process( process( clk, reset) begin begin if reset=‘1’ then if then reg <= ( others others => ‘0’); elsif elsif rising_edge(clk) then then reg <= f(inputs, reg); end if; end if; end process; end process; end architecture arch; end architecture arch; 76

Sequential Logic – VHDL Style 2 architecture arch of architecture arch of disp_mux is is signal signal reg, reg_next : std_logic_vector(N-1 downto downto 0); begin begin process( clk, reset) process( begin begin if if reset=‘1’ then then reg <= ( others others => ‘0’); elsif elsif rising_edge(clk) then then Register update reg <= reg_next; end if; end if; end process; end process; Comb. logic reg_next reg_next <= f(inputs, <= f(inputs, reg reg); ); end architecture arch; end architecture arch; 77

VHDL Variables 78

entity variable_in_process is port ( A,B : in std_logic_vector (3 downto 0); ADD_SUB : in std_logic; S : out std_logic_vector (3 downto 0) ); end variable_in_process; architecture archi of variable_in_process is begin process (A, B, ADD_SUB) variable AUX : std_logic_vector (3 downto 0); begin if ADD_SUB = ’1’ then AUX := A + B ; else AUX := A - B ; end if; S <= AUX; end process; end archi; 79 if-else and if-elsif-else statements use true-false conditions to execute statements. • If the expression evaluates to true , the if branch is executed. • If the expression evaluates to false , x , or z , the else branch is executed. • A block of multiple statements is executed in an if or else branch. • begin and end keywords are required. • if-else statements can be nested.

Differences: Signals vs Variables • Variables can only be declared and used within processes or procedures. Used to hold temporary results . - • Signals can only be declared in architecture. - Used for inter-process communications. • Variables are updated immediately. • Signals are updated after current execution of a process is finished. • Synthesis results: - Variables: similar to signals, but maybe optimized away - Signals: wires, registers, or latches. 80

Differences: Signals vs Variables process (a, b, c, s) process (a, b, c, s) begin begin s <= a and b; o <= s xor c; o <= s xor c; s <= a and b; end process; end process; process (a, b, c) process (a, b, c) variable s : std_logic; variable s : std_logic; begin begin s := a and b; o <= s xor c; o <= s xor c; s := a and b; end process; end process; 81

Differences: Signals vs Variables process (a, b, c, s) begin s <= a and b; o <= s xor c; end process; process (a, b, c) variable s : std_logic; begin s := a and b; o <= s xor c; end process; 82

Differences: Signals vs Variables process (a, b, c) variable s : std_logic; begin o <= s xor c; s := a and b; end process; 83

architecture sig_ex of test is Differences: signal s : std_logic; Signals vs begin process (clk) Variables begin if rising_edge(clk) then s <= a and b; o <= s xor c; end if; end process; end sig_ex; a out1 FF AND b out2 XOR FF c 84

architecture var_ex of test is Differences: begin Signals vs process (clk) Variables variable s : std_logic; begin if rising_edge(clk) then s := a and b; o <= s xor c; end if; end process; end var_ex; a out3 AND b XOR FF out4 c 85

Signals vs Variables – Summary X 1 S 1 C 1 process (clk) begin if rising_edge(clk) then S1 <= C1(X1, S1, S2); S2 <= C2(X2, S1, S2); X 2 end if; S 2 C 2 end process; 86

Signals vs Variables – Summary X 1 V C 1 process (clk) begin if rising_edge(clk) then V := C1(X1, S); S <= C2(X2, S); X 2 end if; S C 2 end process; 87

Case Studies

Stopwatch

Stopwatch 00.0 00.1 00.9 01.0 99.9 ... ... AB.C • A : count of 10 seconds; • B : count of 1 seconds; • C : count of 0.1 seconds. How to measure 0.1 second? 90

Stopwatch – Concept d2 d1 d0 ms d2_en d1_en Msec Msec tick Second10 Second Tick Counter Counter Counter Gen go clk 91

Stopwatch – VHDL Code library library ieee; use use ieee.std_logic_1164. all; all; use use ieee.numeric_std. all all; entity entity stop_watch is is port (clk, go, clr port : in in std_logic; d0 : out out std_logic_vector(3 downto downto 0); d1 : out out std_logic_vector(3 downto downto 0); d2 : out out std_logic_vector(3 downto downto 0)); end entity stop_watch; end entity 92

Stopwatch – VHDL Code architecture architecture caecade_arch caecade_arch of of stop_watch stop_watch is is constant DVSR : integer := 10000000; constant DVSR : integer := 10000000; signal ms_reg signal ms_reg, , ms_next ms_next : unsigned(23 : unsigned(23 downto downto 0); 0); signal d0_reg, d1_reg, d2_reg signal d0_reg, d1_reg, d2_reg : unsigned(3 downto : unsigned(3 downto 0); 0); signal d0_next, d1_next, d2_next signal d0_next, d1_next, d2_next : unsigned(3 : unsigned(3 downto downto 0); 0); signal d1_en, d2_en : std_logic signal d1_en, d2_en : std_logic; signal signal ms_tick ms_tick, d0_tick, d1_tick, d2_tick , d0_tick, d1_tick, d2_tick : : std_logic std_logic; begin begin -- to continue on the next slide -- to continue on the next slide 93

Stopwatch – VHDL Code architecture architecture caecade_arch caecade_arch of of stop_watch stop_watch is is ... –- see previous slide ... see previous slide begin begin -- -- register update register update process(clk process( clk) begin begin if if rising_edge rising_edge(clk clk) then ) then ms_reg <= ms_reg <= ms_next ms_next; d0_reg <= d0_next; d0_reg <= d0_next; d1_reg <= d1_next; d1_reg <= d1_next; d2_reg <= d2_next; d2_reg <= d2_next; end if; end if; end process; end process; 94

Stopwatch – VHDL Code -- -- next state logic next state logic -- -- 0.1 sec tick generator 0.1 sec tick generator ms_next <= (others =>’0’) when ms_next <= (others =>’0’) when clr clr=‘1’ or =‘1’ or (ms_reg ms_reg=DVSR and go=‘1’) else =DVSR and go=‘1’) else ms_reg+1 when go=‘1’ else ms_reg+1 when go=‘1’ else ms_reg; ms_reg ms_tick <= ms_tick <= ms_reg ms_reg=DVSR; =DVSR; -- -- generate generate ms_tick ms_tick -- -- 0.1 second counter 0.1 second counter do_next <= “0000” when do_next <= “0000” when clr clr=‘1’ or =‘1’ or (ms_tick ms_tick=‘1’ and d0_reg=9) else =‘1’ and d0_reg=9) else d0_reg+1 when d0_reg+1 when ms_tick ms_tick=‘1’ else =‘1’ else d0_reg; d0_reg; d0_tick <= d0_reg=9; d0_tick <= d0_reg=9; 95

Stopwatch – VHDL Code -- -- next state logic next state logic -- -- 1 sec counter 1 sec counter d1_en <= ms_tick d1_en <= ms_tick=‘1’ and d0_tick=‘1’; =‘1’ and d0_tick=‘1’; d1_next <= “0000” when d1_next <= “0000” when clr clr=‘1’ or =‘1’ or (d1_en=‘1’ and d1_reg=9) else (d1_en=‘1’ and d1_reg=9) else d1_reg+1 when d1_en=‘1’ else d1_reg+1 when d1_en=‘1’ else d1_reg; d1_reg; d1_tick <= d1_reg=9; d1_tick <= d1_reg=9; -- -- 10 second counter 10 second counter d2_en <= d1_en and d1_tick=‘1’; d2_en <= d1_en and d1_tick=‘1’; d2_next <= “0000” when d2_next <= “0000” when clr clr=‘1’ or =‘1’ or (d2_en=‘1’ and d2_reg=9) else (d2_en=‘1’ and d2_reg=9) else d2_reg+1 when d2_en=‘1’ else d2_reg+1 when d2_en=‘1’ else d2_reg; d2_reg; 96

Stopwatch – VHDL Code -- -- output logic output logic d0 <= d0_reg; d0 <= d0_reg; d1 <= d1_reg; d1 <= d1_reg; d2 <= d2_reg; d2 <= d2_reg; end architecture cascade; end architecture cascade; 97

Non-Synthesizable VHDL

Testbench Code -- clock generator process begin clk <= ‘0’; wait for 10ns; clk <= ‘1’; wait for 10ns; end process; 99

Testbench Code -- test vector generator process process begin begin -- initialization wait until wait until falling_edge(clk); -- generate some random inputs wait until wait until rising_edge(clk); -- generate other random inputs end process end process ; 100