CDA 4253/CIS 6930 FPGA System Design Modeling of Combinational - PowerPoint PPT Presentation

CDA 4253/CIS 6930 FPGA System Design Modeling of Combinational Circuits Hao Zheng Dept of Comp Sci & Eng USF

Reading ➜ P. Chu, FPGA Prototyping by VHDL Examples ➺ Chapter 3, RT-level combinational circuit ➺ Sections 3.1 - 3.2, 3.5 - 3.7. ➜ XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices ➺ Chapter 3 and 7 2

VHDL Model Template: Recap library library ieee ieee; use ieee.std_logic_1164.all; use ieee.std_logic_1164.all; entity entity entity_name entity_name is is port declarations port declarations end [entity] entity_name end [entity] entity_name ; ARCHITECTURE ARCHITECTURE architecture_name OF OF entity_name IS IS Signal & component declarations Signal & component declarations BEGIN BEGIN Concurrent statements Concurrent statements END [ARCHITECTURE] architecture_name ; END [ARCHITECTURE] 3

Concurrent Statements ➜ Simple concurrent signal assignment ➺ z <= a xor b ➜ Conditional signal assignment (when-else) ➜ selected concurrent signal assignment (with- select-when) ➜ Process statements ➺ To be covered later 4

VHDL Modeling Styles VHDL Descriptions • Testbenches behavioral dataflow structural Components and Concurrent Sequential statements interconnects statements • Registers • State machines • Instruction decoders Subset most suitable for synthesis 5

Combinational Circuit Building Blocks 6

Fixed Shifters & Rotators 7

Fixed Logical Shift Right in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO SIGNAL DOWNTO 0); SIGNAL C : STD_LOGIC_VECTOR(3 DOWNTO SIGNAL DOWNTO 0); A(3) A(2) A(1) A(0) 4 A A A srl A srl 1 C C 4 � 0 � A(3) A(2) A(1) srl : logic shift right C <= A C <= A srl srl 1; 1; srl C <= ‘0’ & A(3 downto C <= ‘0’ & A(3 downto 1); 1); 8

Fixed Arithmetic Shift Right in VHDL SIGNAL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO DOWNTO 0); SIGNAL SIGNAL C : STD_LOGIC_VECTOR(3 DOWNTO DOWNTO 0); A(3) A(2) A(1) A(0) 4 A A A sra A sra 1 C C 4 A(3) A(3) A(2) A(1) C <= A sra C <= A sra 1; 1; sra : arithmetic shift left sra c <= A(3) & A(3 downto c <= A(3) & A(3 downto 1); 1); 9

Fixed Rotation in VHDL SIGNAL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO DOWNTO 0); SIGNAL C : STD_LOGIC_VECTOR(3 DOWNTO SIGNAL DOWNTO 0); A(3) A(2) A(1) A(0) 4 A A A rol A rol 1 C C 4 A(2) A(1) A(0) A(3) C <= A rol 1 rol rol: : rotation to left 10

Logic Gates 11

Basic Gates – AND, OR, NOT x 1 x 2 x 2 … x 1 � � � � x 1 x x 1 x 2 n x 2 x n (a) AND gates x 1 x 2 x 1 2 … x x 1 x + x 1 x + + + 2 n x 2 x n (b) OR gates x x (c) NOT gate 12

Basic Gates – NAND, NOR x 1 x 2 x 1 × × … × × x 1 x 2 x n x 1 x 2 … x 2 x n (a) NAND gates x 1 x 2 x 1 … x 1 + x 2 x 1 + x 2 + … + x n x 2 x n (b) NOR gates 13

Basic Gates – XOR Å x 1 x f = x x 2 1 2 0 0 0 0 1 1 x 1 1 0 1 Å f = x x 1 2 x 2 1 1 0 (a) Truth table (b) Graphical symbol x 1 x 2 Å f = x x 1 2 (c) Sum-of-products implementation 14

Basic Gates – XNOR Å x 1 x f = x x 2 1 2 0 0 1 0 1 0 x 1 . 1 0 0 Å f = x x = x x 1 2 x 1 2 2 1 1 1 (a) Truth table (b) Graphical symbol x 1 x 2 Å f = x x 1 2 (c) Sum-of-products implementation 15

1-Bit Full Adder x y s cin cout 16

1-Bit Full Adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY ENTITY fa1b IS IS PORT PORT ( x : IN IN STD_LOGIC ; y : IN IN STD_LOGIC ; cin : IN IN STD_LOGIC ; s : OUT OUT STD_LOGIC ; cout : OUT OUT STD_LOGIC ) ; END END fa1b; 17

1-Bit Full Adder ARCHITECTURE ARCHITECTURE dataflow OF OF fa1b IS IS BEGIN BEGIN s <= x XOR XOR y XOR XOR cin ; cout <= (x AND AND y) OR OR (cin AND AND x) OR OR (cin AND AND y) ; END END dataflow ; x s y cin cout 18

Logic Operators • Logic operators and or and or nand nand nor nor xor xor not xnor not xnor • Logic operators precedence Highest not not and or and or nand nand nor nor xor xor xnor xnor Lowest 19

No Implied Precedence Wanted: y = ab + cd Incorrect y <= a and b or c and d; equivalent to y <= ((a and b) or c) and d; equivalent to y = (ab + c)d Correct y <= (a and b) or (c and d); 20

Modeling Routing Structures with Conditional Concurrent Signal Assignment (when-else) 21

2-to-1 Multiplexer sel f sel w 0 w 0 0 0 f w 1 1 w 1 1 (a) Graphical symbol (b) Truth table 22

2-to-1 Multiplexer LIBRARY ieee ; LIBRARY USE ieee.std_logic_1164.all ; USE ENTITY ENTITY mux2to1 IS IS PORT PORT ( w0, w1, sel : IN IN STD_LOGIC ; f : OUT STD_LOGIC ) ; OUT END mux2to1 ; END ARCHITECTURE ARCHITECTURE dataflow OF OF mux2to1 IS IS BEGIN BEGIN f <= f <= w0 WHEN w0 WHEN sel sel = '0' ELSE = '0' ELSE w1; w1; END dataflow ; END 23

Conditional Concurrent Signal Assignment target_signal <= value1 when when condition1 else else value2 when when condition2 else else . . . value N+1 when when condition N+1 else else value N ; ➜ Branches are evaluated one by one from top to bottom. ➜ Induces priority among branches 24

Cascade of Multiplexers LIBRARY ieee ; LIBRARY USE USE ieee.std_logic_1164.all ; ENTITY ENTITY mux_cascade IS PORT (w1, w2, w3 PORT : IN STD_LOGIC ; s1, s2 : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux_cascade ; END ARCHITECTURE dataflow OF ARCHITECTURE OF mux_cascade IS IS BEGIN BEGIN w1 WHEN s1 = � 1' f <= f <= w1 WHEN s1 = 1' ELSE ELSE w2 WHEN s2 = � 1 � w2 WHEN s2 = ELSE ELSE w3; w3; END dataflow ; END 25

Cascade of Multiplexers w 2 0 0 w 3 1 y w 1 1 s 1 s 2 Notice the priority of selection. 26

Conditional Concurrent Signal Assignment target_signal <= value1 when condition1 else when else value2 when condition2 else when else . . . value N+1 when when condition N+1 else else value N ; 0 … Value N .… 0 1 0 Value N-1 1 Target Signal 1 Value 2 Value 1 Condition N-1 Condition 2 Condition 1 27

More Operators • Relational operators = /= < <= > >= = /= < <= > >= • Logic and relational operators precedence Highest not not = /= < <= > >= = /= < <= > >= and or and or nand nand nor nor xor xor xnor xnor Lowest 28

Precedence of Logic and Relational Operators Comparison a = bc Incorrect … when a = b and and c else … equivalent to … when (a = b) and and c else … Correct … when a = (b and and c) else … 29

Modeling Routing Structures with Selected Concurrent Signal Assignment (with-select-when) 30

4-to-1 Multiplexer s 0 s 1 s 1 s f 0 w w 00 0 0 0 0 w 01 w 1 0 1 f 1 w 10 w 2 1 0 2 w 11 3 w 1 1 3 (b) Truth table (a) Graphic symbol No priority, and choices are disjoint. 31

A 4-to-1 Multiplexer LIBRARY LIBRARY ieee ; USE USE ieee.std_logic_1164. all all ; ENTITY ENTITY mux4to1 IS IS PORT( PORT( w0, w1, w2, w3 : IN IN STD_LOGIC ; s : IN IN STD_LOGIC_VECTOR(1 DOWNTO DOWNTO 0); f : OUT OUT STD_LOGIC ) ; END mux4to1 ; END ARCHITECTURE ARCHITECTURE dataflow OF OF mux4to1 IS IS BEGIN BEGIN WITH WITH s SELECT SELECT default condition f <= w0 WHEN WHEN "00", w1 WHEN WHEN "01", w2 WHEN WHEN "10", w3 WHEN WHEN OTHERS OTHERS ; END END dataflow; 32

Selected Concurrent Signal Assignment with choice_expression select target <= expression1 when choices_1 , expression2 when choices_2 , . . . expressionN when choices_N ; All choices are mutually exclusive and cover all values of choice_expression. 33

Selected Concurrent Signal Assignment with choice_expression select target <= expression1 when choices_1 , expression2 when choices_2 , . . . expressionN when choices_N ; expression1 choices_1 expression2 choices_2 target_signal expressionN choices_N choice expression 34

Formats of Choices • when Expr when Expr _1 | .... | Expr_ N • this branch is taken if any of Expr _x matches • choice_expression when others when others • 35

Formats of Choices - Example with with sel select select y <= a when when "000", c when when "001" | "111", d when when others others ; 36

Decoders 37

2-to-4 Decoder w w y y y y En 1 0 3 2 1 0 w y 1 3 1 1 0 0 0 0 0 w y 0 2 0 1 0 0 1 0 1 y 1 1 1 0 0 1 0 0 y En 0 1 1 1 1 0 0 0 x x 0 0 0 0 0 (a) Truth table (b) Graphical symbol 38

VHDL Code for a 2-to-4 Decoder -- LIBRARY not shown ENTITY ENTITY dec2to4 IS IS PORT PORT ( w : IN IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN IN STD_LOGIC ; y : OUT OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END END dec2to4 ; ARCHITECTURE ARCHITECTURE dataflow OF OF dec2to4 IS IS SIGNAL SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO DOWNTO 0) ; BEGIN BEGIN Enw <= En & w ; WITH Enw SELECT WITH SELECT � 0001" WHEN WHEN "100", y <= WHEN "101", "0010" WHEN WHEN "110", "0100" WHEN � 1000" WHEN WHEN "111", OTHERS ; "0000" WHEN WHEN OTHERS END END dataflow ; 39

Encoders 40