Clock IC Product Update Clock IC Product Update Clock Distribution - - PowerPoint PPT Presentation

The World Leader in High-Performance Signal Processing Solutions

Clock IC Product Update Clock IC Product Update

Clock Distribution and Clock Generation Solutions Clock Distribution and Clock Generation Solutions September 2005 September 2005

2

Dimensions of Clock and Timing ICs

Not so Obvious Not so Obvious Channel Isolation Channel Isolation RF Interference RF Interference Slew Rate Slew Rate Design Tools Design Tools Synchronization Synchronization Line Terminations Line Terminations External Oscillators External Oscillators Obvious Obvious Speed Speed Edge Skew Edge Skew Jitter Jitter Phase Noise Phase Noise

3

ADI Clock IC Innovations for Cost

Small Packages Small Packages

32 LFCSP 32 LFCSP 5mm x 5mm 5mm x 5mm Saves board Saves board space space

Design Tools Design Tools

Before you even step Before you even step foot into the lab foot into the lab… …

• design clock circuit

design clock circuit

• select components

select components

• test ideas

test ideas

• check performance

check performance … … save time and money save time and money

Clean Interfaces, Ease of Use Clean Interfaces, Ease of Use

Differential LVPECL for Differential LVPECL for chip chip-

• to

to-

• chip signals.

chip signals. AD9513/14/15 have AD9513/14/15 have pin pin-

• programmable

programmable divides, phase, delay divides, phase, delay… … no serial port required no serial port required

4

Signal Signal-

• to

to-

• Noise Ratio in Data Converters

Noise Ratio in Data Converters

www.analog.com/clocks 5

Clock Jitter/Phase Noise can reduce SNR in data converters

ADC DAC

Analog Input Sampling Clock SNR Analog Output (after LPF) Sampling Clock Digital Output SNR Digital Input

Why ADI must advance performance clocks

www.analog.com/clocks 6

ADCs perform great in the lab…

Ain=165 MHz Encode=80 MSPS SNR=71.78 dB 6 layer board

2 signal 2 ground 2 power

Good Clock Source Jitter ~0.15 ps

www.analog.com/clocks 7

…but in a real application!

Ain=165 MHz Encode=80 MSPS SNR=58.88 dB 6 layer board

2 signal 2 ground 2 power

Typical Gate, High Speed CMOS Jitter ~0.8 ps

www.analog.com/clocks 8

Jitter – A common noise source introduced at the SHA in A-D Converter

Clock jitter is the sample to sample

variation in the encode clock (both the external jitter as well as the internal jitter).

Fullscale SNR is jitter limited by: See AN-501 and new AN-756

SHA = Sample & Hold Amplifier SNR = Signal to Noise Ratio

Encode dV error voltage

        =         =

jitter rms rms jitter

ft N S SNR π 2 1 log 20 log 20

www.analog.com/clocks 9

Looking for RMS clock jitter in 0.1-2ps range

30 40 50 60 70 80 90 100 110 120 130 1 10 100 1000 Input in MHz SNR in dB

16 bits 14 bits 12 bits 10 bits .125 pS .25 pS 2 pS .5 pS 1 pS

Want to use ADI data converters here Analog Freq 70-300MHz, SNR 60-80dB RMS Jitter < 1ps is very high performance

10

Clock Products in production

48 LFCSP Serial 0.7 total CML Analog 655 2 655 +1.8V & +3.3V PLL Core Generation AD9540 32 LFCSP Pin Select 0.225 additive LVPECL LVDS CMOS 1600 2 1600 +3.3V No Distribution AD9515 32 LFCSP Pin Select 0.225 additive LVPECL LVDS CMOS 1600 3 1600 +3.3V No Distribution AD9514 32 LFCSP Pin Select 0.3 additive LVDS CMOS 800 3 1600 +3.3V No Distribution AD9513 48 LFCSP Serial 0.25 additive LVPECL LVDS CMOS 1200 5 1600 +3.3V No Distribution AD9512 48 LFCSP Serial 0.25 additive LVPECL LVDS CMOS 1200 5 1600 +3.3V PLL Core Distribution AD9511 64 LFCSP Serial 0.25 additive LVPECL LVDS CMOS 1200 8 1600 +3.3V PLL Core Distribution AD9510 Package I/O Interface Random Jitter (ps rms) Output Logic Max Output Frequency (MHz)

• No. of

Outputs Max Input Frequency (MHz) Voltage Supply (V) On-Chip Multiplier Primary Clock Function Part#

11

AD9516 AD9516

12

Clock ICs with on-chip VCOs

REFINB CLK1 CLK1B SCLK SDIO SDO CSB FUNCTION

CHARGE PUMP

OUT0 OUT0B L F

SERIAL CONT ROL PORT (Default)

OUT3 OUT3B

PHASE FREQUENCY DET ECT OR R DIVIDER DIVIDE BY 1 T O 32

BYPA SS REFIN CP

P, P+1 PRESCALER

OUT9 OUT9B

SYNCB, RESET B DIVIDE BY 1 T O 32

OUT8 OUT8B LVDS/CMOS OUT2 OUT2B OUT1 OUT1B VCP VS GND STA TUS CPRSET

DIST REF

RSET

PLL REF LOW DROPOUT REGULAT OR (LDO) LINEAR BUFFER DIVIDE BY 2,3,4,5,

• r

6 OSC OUT A/B COUNT ERS PROGRAMMABLE "N" DELAY PROGRAMMABLE "R" DELAY

OUT5 OUT5B OUT4 OUT4B

DIVIDE BY 1 T O 32 DIVIDE BY 1 T O 32

OUT7 OUT7B

DIVIDE BY 1 T O 32

OUT6 OUT6B LVDS/CMOS DLD PDB LVPECL

N DIVIDER

LVPECL LVPECL

VIN

LOR

CHECK REFIN CHECK PFD POWER DOWN CHECK INT ERNAL LEVELS DIVIDE BY 1 T O 32 DIVIDE BY 1 T O 32

∆T ∆T ∆T ∆T

AD9516

Featured in block diagram, AD9516, is in Featured in block diagram, AD9516, is in development now with samples in Feb. 06 development now with samples in Feb. 06

DIVIDERS w/PHASE OFFSET DELAY ADJUST

ADI Clock ICs continue to ADI Clock ICs continue to integrate high value functions to integrate high value functions to lower system cost: lower system cost:

• complete PLL w/on

complete PLL w/on-

• chip VCO

chip VCO

• 5 programmable dividers

5 programmable dividers

• 4 programmable delay lines

4 programmable delay lines

• 10 clock outputs synchronized

10 clock outputs synchronized to input reference to input reference

www.analog.com/clocks 13

AD9516 Summary 1.6GHz Clock Distribution IC with on-chip VCO

Low noise PLL with on-chip VCO Low Jitter Clock Distribution Low Skew Clock Outputs 10 Clock Outputs

Six LVPECL at 1.6GHz Four LVDS/CMOS at 800/250MHz

Programmable Dividers Programmable Phase Offset Four Fine Delay Adjust Elements 64 LFCSP Package pin-similar to AD9510

• 40°C to +85°C operation

3.3V Core supply LVPECL Outputs 2.5V, 3.3V compatible

In Development Now In Development Now Samples Feb. Samples Feb. ‘ ‘06 06

14

ADI in Clock Distribution

ADC

AD9510 Clock Distribution IC

ADC ADC ADC DDC or ASIC DAC DUC or FPGA DAC

User’s Reference Clock Clock to A-D Converters Clock to D-A Converters Clock to Digital Chips

ADI Clock Distribution ICs lower overall ADI Clock Distribution ICs lower overall system noise: system noise:

• clocks with sub

clocks with sub-

• picosecond jitter

picosecond jitter

• best

best-

• in

in-

• class channel isolation

class channel isolation

• clean

clean-

• up jitter on user

up jitter on user’ ’s input reference s input reference

15

ADC ADC FIFO FIFO

122.88 MHz 122.88 MHz 122.88 MHz 122.88 MHz

LVPECL LVPECL CMOS CMOS

DELAY = 4.3ns DELAY = 4.3ns HIGH PRECISION MEASUREMENT SUBSYSTEM HIGH PRECISION MEASUREMENT SUBSYSTEM

VCXO VCXO

LOOP LOOP FILTER FILTER

REFCLK REFCLK 491.52 MHz 491.52 MHz

LVPECL LVPECL

30.72 MHz 30.72 MHz

DAC DAC DAC DAC FPGA FPGA

LVDS LVDS CMOS CMOS CMOS CMOS

QUADRATURE TRANSMIT SOURCE QUADRATURE TRANSMIT SOURCE 61.44 MHz 61.44 MHz 61.44 MHz 61.44 MHz PHASE = 90 PHASE = 90° ° DELAY = 10ns DELAY = 10ns 122.88 122.88 MHz MHz

LVPECL LVPECL

491.52 MHz 491.52 MHz CLEAN_REFCLK CLEAN_REFCLK 30.72 MHz 30.72 MHz CALIBRATION CALIBRATION 15.36 MHz 15.36 MHz

ADI clock ICs simplify board ADI clock ICs simplify board design by integrating phase design by integrating phase control, delay adjust, frequency control, delay adjust, frequency dividers and logic translation dividers and logic translation

PHASE = 0 PHASE = 0° °

TOYOCOM TOYOCOM 491.52 491.52

16

ADI in Clock Generation

AD9540 Clock Generation IC

Clock Path A

Synchronize to User reference clock

• r

Use fixed 25MHz crystal Frequency = 38.88 MHz

ADI Clock Generation ICs combine low jitter, with fine ADI Clock Generation ICs combine low jitter, with fine phase and frequency control. The output clocks may phase and frequency control. The output clocks may be programmed to 1 part in 2 be programmed to 1 part in 248

48 resulting in micro

resulting in micro-

• Hertz

Hertz frequency resolution. frequency resolution.

Clock Path B

Frequency = 622.08 MHz

Clock Generation ICs have multiple configuration options to lock two different frequencies to a single reference, while maintaining low jitter and precise synchronization

17

Combine clock generation with clock distribution for a complete timing solution

AD9540 DC to 655 MHz Low Jitter Frequency Source Output may be synchronized to external reference. Combine with AD9512 Clock Distribution chip for 5 Output Clocks Programmable Divide Ratio, Phase Select and Delay Adjust Reference

• r

Cystal AD9512

LF

ADI Clock ICs offer designers a complete ADI Clock ICs offer designers a complete solution: solution:

• Precise Clock Generation

Precise Clock Generation

• Low Jitter Clock Distribution

Low Jitter Clock Distribution

• Optimized interface between timing ICs

Optimized interface between timing ICs

18

ADI Announces ADIsimCLK version 1.1

ANALOG DEVICES ANALOG DEVICES’ ’ NEW CIRCUIT SIMULATION TOOL SIMPLIFIES CLOCK DESIGN FOR COMMUNI NEW CIRCUIT SIMULATION TOOL SIMPLIFIES CLOCK DESIGN FOR COMMUNICATIONS, CATIONS, IMAGING, AND INSTRUMENTATION APPLICATIONS IMAGING, AND INSTRUMENTATION APPLICATIONS Norwood, MA(8/23/2005) Norwood, MA(8/23/2005) -

• Analog Devices, Inc. (NYSE:

Analog Devices, Inc. (NYSE: ADI ADI), a global leader ), a global leader in high in high-

• performance semiconductors for signal processing applications, t

performance semiconductors for signal processing applications, today

• day

announced the availability of its new announced the availability of its new ADIsimCLK ADIsimCLK™ ™ clock IC design and clock IC design and simulation tool, along with the addition of three new clock ICs simulation tool, along with the addition of three new clock ICs to its growing to its growing portfolio of clock products. ADIsimCLK offers clock and timing e portfolio of clock products. ADIsimCLK offers clock and timing engineers an ngineers an easy easy-

• to

to-

• use simulation tool for designing and analyzing clock circuits u

use simulation tool for designing and analyzing clock circuits used in a sed in a broad range of applications, such as wireless transceivers, broa broad range of applications, such as wireless transceivers, broadband dband infrastructure, medical imaging, general instrumentation, and au infrastructure, medical imaging, general instrumentation, and automated test tomated test

• equipment. By using the tool
• equipment. By using the tool’

’s tutorials, design wizards, and user s tutorials, design wizards, and user-

• friendly data

friendly data entry screens, engineers can now create complete, robust timing entry screens, engineers can now create complete, robust timing solutions in solutions in

• minutes. And because ADIsimCLK models the phase noise and jitter
• minutes. And because ADIsimCLK models the phase noise and jitter of the
• f the

components used, final system performance can be predicted with components used, final system performance can be predicted with great great accuracy, allowing designers to move from simulations to final b accuracy, allowing designers to move from simulations to final board layouts

• ard layouts

faster, removing iterations from the design process and speeding faster, removing iterations from the design process and speeding time to time to

• market. The new tool is offered as a free download from
• market. The new tool is offered as a free download from ADI

ADI’ ’s website s website. .

ADIsimCLK Features Easy-To-Use, Tutorials, Design Wizards, Reference Designs, VCO/VCXO Library, PLL Design, Loop Filter Design, Accurate Phase Noise Models

19

ADI Introduces Three New Members of Clock Distribution Family

MiniDivider Family MiniDivider Family

Pin programmable Pin programmable Range of Divide Ratios Range of Divide Ratios Selectable Phase Offset Selectable Phase Offset Fine Delay Adjust Fine Delay Adjust < 300 femtoseconds rms jitter < 300 femtoseconds rms jitter Excellent output isolation Excellent output isolation

AD9513 AD9513

800 MHz Clock Distribution 800 MHz Clock Distribution Three Outputs LVDS/CMOS Three Outputs LVDS/CMOS

AD9514 AD9514

1.6 GHz Clock Distribution 1.6 GHz Clock Distribution Two Outputs LVPECL Two Outputs LVPECL One Output LVDS/CMOS One Output LVDS/CMOS

AD9515 AD9515

1.6 GHz Clock Distribution 1.6 GHz Clock Distribution One Output LVPECL One Output LVPECL One Output LVDS/CMOS One Output LVDS/CMOS

20

AD9513/14/15 Key Features

All three chips can receive input clocks up to 1.6 GHz 1.6 GHz LVPECL clock outputs have 225 femtoseconds (fs) broadband

additive rms jitter

800 MHz LVDS and 250 MHz CMOS clock outputs also have excellent jitter

performance at 300 fs rms and 290 fs rms respectively

All chips characterized for output isolation to adjacent clock channels.

ADI clock chips maintain low jitter even when clock outputs are programmed for different frequencies (e.g. OUT0 divide by 2, OUT1 divide by 8 etc).

Ease of use, no serial port required – all three products are programmed

by connecting S10-S0 pins to GND, VREF, (NC), or VS

Divide ratios in range of 1-32 available on each channel Phase offset available on each channel Adjustable delay (fullscale 1.5ns-10ns) on one channel Small 5mm x 5mm package, 32 LFCSP

21

AD9510 1.2 GHz, 8-Channel Clock Distribution IC

Clock Outputs Clock Outputs 1.2 GHz LVPECL 1.2 GHz LVPECL 800 MHz LVDS 800 MHz LVDS 250 MHz CMOS 250 MHz CMOS PLL Core PLL Core 250 MHz REFIN 250 MHz REFIN 1.6 GHz PLL 1.6 GHz PLL Jitter Clean Jitter Clean-

• up

up Programmable Dividers Programmable Dividers Any integer 1 to 32 Any integer 1 to 32 Phase offset control Phase offset control Each divider independent Each divider independent Programmable Delay Adjust Programmable Delay Adjust Fullscale from 1ns to 10ns Fullscale from 1ns to 10ns 32 delay steps 32 delay steps

64 64-

• LFCSP

LFCSP typically replaces typically replaces Five(5) discrete ICs Five(5) discrete ICs

22

AD9510 integrates LVPECL clocks with adjustable LVDS/CMOS clocks to reduce system cost

AD9510 uses external VCO or AD9510 uses external VCO or VCXO to form complete PLL VCXO to form complete PLL VCXO advantages VCXO advantages

• stability

stability

• frequency range, <100ppm

frequency range, <100ppm

• power up to known state

power up to known state

ADC Digital ASIC IF 170 MHz

A B Low jitter < 250fs

SNR

100 MHz

71.4 dB

DA T A DATA C Jitter-limited signal to noise ratio

Loop Filter VCXO

500 MHz

LVPECL low jitter ADC clock & LVPECL low jitter ADC clock & LVDS/CMOS adjustable delay LVDS/CMOS adjustable delay ASIC clock offer complete solution ASIC clock offer complete solution

A B C

ADC clock ASIC clock ADC data ASIC captures ADC data

CP DIVIDE 1-32 PFD R DIVIDE 1-32 N DIVIDE 1-32 DIVIDE 1-32 DIVIDE 1-32 DIVIDE 1-32 DIVIDE 1-32 ∆T DIVIDE 1-32 ∆T SERIAL PORT

23

AD9510 – Additive Phase Noise Plot

AD9510 AD9510 Additive Phase Noise Additive Phase Noise

24

ADIsimCLK ADIsimCLK

25

Clock Design and Simulation Tool

Easy-To-Use Tutorials Design Wizards Reference Designs VCO/VCXO Library PLL Design Loop Filter Design Accurate Models Free download from ADI website: www.analog.com/ADIsimCLK

• Will continue to add new products
• Will continue to update functionality
• Current version is 1.1

26

ADIsimCLK PLL Configuration Options

(A) INTEGRATED PLL WITH CLOCK CLEANUP, FREQUENCY TRANSLATION AND CLOCK DISTRIBUTION (B) ADDING AND EXTERNAL FILTER TO (A) FOR LOWER PHASE NOISE (C) CLOCK DISTRIBUTION CIRCUIT ONLY

27

ADIsimCLK Distribution Configuration

28

ADIsimCLK includes Timing View

29

ADIsimCLK analysis for each clock output