[PDF] - DR PMC/XMC 16-Channel Wide Band Receiver 125 MSPS Sampling PDF Document

SLIDE 1

Velocia PMC Modules

Innovative Integration | 805.578.4260 | www.innovative-dsp.com

Overview

Description
DR PMC/XMC

Applications

Features

16-Channel Wide Band Receiver 125 MSPS Sampling GC5016 Digital Down Converters

Xilinx Virtex2 Pro FPGA for User Code

Ordering Information

SLIDE 2

Velocia PMC Modules

Innovative Integration | 805.578.4260 | www.innovative-dsp.com

DR Velocia PMC/XMC Module

Software and Logic Framework – Custom

Logic Support

Clock

Manager

Ext B Ext A Low Jitter Switch (SW Config) Clock Driver Divide 1,2,3,4 To ADC To FPGA To FPGA PLL (5ps jitter) A A/B A/B PLL Out A/B 14.4MHz Ref Clock

External Clock External Clock Clock Manager P4 42 pins XMC Links 800 MB/s 4x Rocket I/O PCI 32/64 bit 33/66 MHz

Virtex - II Pro (VP40 or VP50) Virtex - II Pro

FIFO In/Out PCI Precision Crystal Oscillator User Configurable Logic Clock Control FIFO LVDS/TTL Select Map FIFO

Ext. Clocks

& Triggers ZBT SBSRAM 2 MB Memory Management 1 of 4 1 of 4 A/D 125 MSPS LTC2255 FIFO DDC 125 MHz GC 5016 Flash ROM PLL 31-700 MHz PPC PPC DDR SDRAM 64 MB Command Channel Error Correction Rocket I/O

SLIDE 3

Velocia PMC Modules

Innovative Integration | 805.578.4260 | www.innovative-dsp.com

Software Support
OEM Configurations
Analog Performance Characteristics

DR Velocia PMC/XMC Module

1

160
140
120
100
80
60
40
20

50 100 150 200 250 300 350 400 450 500 550

dB KHz

Ch 0 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 Ch 9 Ch 10 Ch 11 Ch 12 Ch 13 Ch 14 Ch 15 Ch 16 Ch 17 Ch 18 Ch 19

Intermodulation Distortion 4.9 & 5.1 MHz

fs= 118.8MHz

Crosstalk

160
140
120
100
80
60
40

50 100 150 200 250 300 350 400 450 500 550

Max S/N (dB) S/N (dB) SINAD (dB) ENOB SFDR (dB) THD (%/dB) 98.1 0.0 0.0 0.0 0.0 0.000000 (0.0dB)

dB KHz

Ch 0 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 Ch

fs= 122.4MHz Ch 0 = -1 dB BFS, 100MHz Ch1 grounded

9 Ch 10 Ch 11 Ch 12 Ch 13 Ch 14 Ch 15 Ch 16 Ch 17 Ch 18 Ch 19

Signal Quality

PMC DR 122.4 MSPS 1.955 MHz Input, -3dB 1 2 3 4 5 6

130
120
110
100
90
80
70
60
50
40
30
20
10

5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 Max S/N (dB) S/N (dB) SINAD (dB) ENOB SFDR (dB) THD (%/dB) 86.0 69.2 68.3 11.0 89.7 0.004061 (87.8dB)

dB KHz

Ch 0

SLIDE 4

Velocia PMC Modules

Innovative Integration | 805.578.4260 | www.innovative-dsp.com

Signal Quality @ 10MHz

PMC DR 10 MHz input, -3dB FS 122.4 MSPS 1 2 3 4

130
120
110
100
90
80
70
60
50
40
30
20
10

5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 Max S/N (dB) S/N (dB) SINAD (dB) ENOB SFDR (dB) THD (%/dB) 86.0 62.6 51.6 8.3 57.2 0.189907 (54.4dB)

dB KHz

Ch 0

Signal Quality @ 350MHz

PMC DR 350 MHz, -3dB FS input 122.4 MSPS 1 2 3 4 5 6

130
120
110
100
90
80
70
60
50
40
30
20
10

5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 Max S/N (dB) S/N (dB) SINAD (dB) ENOB SFDR (dB) THD (%/dB) 86.0 36.7 35.6 5.6 44.3 0.205708 (53.7dB)

dB KHz

Ch 0

Signal Quality @ 100MHz

PMC DR 100 MHz, -3dB FS 122.4 MSPS 1 2

130
120
110
100
90
80
70
60
50
40
30
20
10

5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 Max S/N (dB) S/N (dB) SINAD (dB) ENOB SFDR (dB) THD (%/dB) 86.0 43.0 39.9 6.3 53.5 0.301438 (50.4dB)

dB KHz

Ch 0

DR Velocia PMC/XMC Module

SLIDE 5

Velocia PMC Modules

Innovative Integration | 805.578.4260 | www.innovative-dsp.com

DR Velocia PMC/XMC Module

SLIDE 6

Velocia PMC Modules

Innovative Integration | 805.578.4260 | www.innovative-dsp.com

Analog Input

Digital Down-Converters
Time Base and Triggers
Application-Configurable Logic
PCI-FPGA
Memory
XMC
PCI Interface
DR Velocia PMC/XMC Module Technical Specifications

Debug Ports

Connectors
Power
Operating Conditions
Development Languages
Application Software
Physicals
Accessories
Documentation
Environmental Data