Clock Enable Timing Closure Methodology Harish Dangat Samsung - - PowerPoint PPT Presentation

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Clock Enable Timing Closure Methodology Harish Dangat Samsung - - PowerPoint PPT Presentation

Nov 11, 2022 744 likes •1.19k views

Clock Enable Timing Closure Methodology Harish Dangat Samsung Semiconductor (company logo if desired) Agenda Basics of Clock Gating Fixing Clock Enable Timing in RTL-2-GDSII Flow Results Conclusion Harish Dangat 2 Clock

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SLIDE 1

(company logo if desired)

Clock Enable Timing Closure Methodology

Harish Dangat Samsung Semiconductor

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2

Harish Dangat

  • Basics of Clock Gating
  • Fixing Clock Enable Timing in RTL-2-GDSII Flow
  • Results
  • Conclusion

Agenda

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3

Harish Dangat

Clock Gating Basic

  • Use internal (or external)

signal to disable clock

  • This saves Dynamic

Power

  • A must for low power

design

  • Creates new timing paths
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4

Harish Dangat

Two Types of Clock Gating

  • Using AND gate
  • Using ICG Cell

Rest of presentation is about ICG type clock gating

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5

Harish Dangat

Register to Register Path

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6

Harish Dangat

Register to Register Path with Clock Gating

EN D D

CE Path CE clk Path Clock gated clk Path 1ns 1ns 0.5ns

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7

Harish Dangat

What is different about CE path

  • Not noticed at Synthesis
  • Timing available is less than cycle time
  • ICG cells are not skew balanced with registers
  • Violations are seen only after Clock Tree Synthesis
  • Mostly affects timing critical blocks
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8

Harish Dangat

Effect of ICG Cells Location in Clock Tree

Good Location Acceptable Location Potential bad Location CE timing

CLK

Architectural Gaters

0ns 1ns 0.5ns 0.25ns 0.75ns

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9

Harish Dangat

  • Basics of Clock Gating
  • Fixing Clock Enable Timing in RTL-2-GDSII

Flow

  • Results
  • Conclusion

Agenda

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Harish Dangat

  • CE signal should be generated in the same

module

  • Generate CE signal from functionally related

modules

  • Simplify the logic that generates CE signal

What to Do at RTL Level

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11

Harish Dangat

  • Reduce cycle time to ICG cells
  • Set high setup time on ICG cells
  • Turn off bus sharing in Power Compiler

CE Timing at Synthesis Step

set_clock_latency

  • (cycle_time/2) \

[get_pin all_clock_gating_registers/CK] set_clock_latency 0 [get_pin all_clock_gating_registers/ECK] set timing_scgc_override_library_setup_hold true set_clock_gating_style –setup 400ps clock_gate set_clock_gating_style –no_sharing

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Harish Dangat

  • When placing modules, pay attention to CE

signal connectivity

  • If CE signal(s) are input pins, place them close

to modules that receive it

CE Timing at Floorplan Step

CE CE timing problem CE Good CE timing

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13

Harish Dangat

  • Tightening available cycle time by changing ICG

setup time

  • Tightening available cycle time by changing ICG

clock latency

CE Timing at placement Step

set timing_scgc_override_library_setup_hold true set_clock_gating_style –setup 400ps clock_gate set_clock_latency

  • (cycle_time/2) \

[get_pin all_clock_gating_registers/CK] set_clock_latency 0 [get_pin all_clock_gating_registers/ECK]

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14

Harish Dangat

  • Create group path and add extra weight
  • Place ICG cells close to flops

CE Timing at placement Step (cont)

group_path

  • weight 5 -name CLOCK_ENABLE \

–to [get_cell */*GATE_LATCH] set placer_disable_auto_bound_for_gated_clock false

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Harish Dangat

  • Apply global latency

– Easy, Not very efficient

  • Apply based on ICG depth and fanout

– Less depth – more latency – More fanout – more latency

  • Apply based on CTS results

– More accurate

How to Select Latency?

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Harish Dangat

  • Clone ICG Cells

CE Timing at Clock Tree Synthesis

set icg_cells { icg_cell_1 icg_cell_2 } split_clock_net -objects [get_cells $icg_cells] \

  • split_intermediate_level_clock_gates -gate_sizing

remove_ideal_network [all_fanout -flat -clock_tree] remove_propagated_clock * remove_clock_tree

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Harish Dangat

ICG Cloning

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Harish Dangat

CE Timing at Clock Tree Synthesis Cloning based on fanout and slack

foreach_in_collection CELLS [get_cells * -hier -filter "ref_name =~ *ICG*"] { set names [get_object_name $CELLS] set ckPins [get_object_name [get_pins -of_object [get_cells $CELLS] \

  • filter "full_name =~ */CLK"]]

set eckPins [get_object_name [get_pins -of_object [get_cells $CELLS] \

  • filter "full_name =~ */ENABLE_CLK"]]

set eckFanout [sizeof_collection [all_fanout -from [get_pins $eckPins] -flat]] set cgSlack [get_attribute [get_pins ${names}/ENABLE] max_slack if {$cgSlack > -0.150 && $eckFanout > 100} { echo "${names}/E" } remove_propagated_clock * remove_clock_tree

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19

Harish Dangat

CE Timing at Clock Tree Synthesis Two Pass Flow

Clock Tree Synthesis Placement Clone clock tree Write Verilog New Placement

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Harish Dangat

  • Basics of Clock Gating
  • Problems Created by Clock Gating
  • Fixing Clock Enable Timing in RTL-2-GDSII Flow
  • Results
  • Conclusion

Agenda

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Harish Dangat

Die Temperature Without and With Clock Gating

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Harish Dangat

ICG Cells and Flops Autobound

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Harish Dangat

Comparing Latency Schemes

  • 0.6
  • 0.5
  • 0.4
  • 0.3
  • 0.2
  • 0.1

100 200 300 400 500 600 700 800 900 Series1 Series2 Series3

Path CE violation (ns)

Baseline run 1ns latency

Selective latency

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Harish Dangat

Results – Effect on cloning on latency

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 200 400 600 800 1000 1200

Series1 Series2

Without Cloning IC ICG C Clock Latency (n (ns) Path ths (So (Sorted, lo low to to hig high) Wit ith Clo lonin ing

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Harish Dangat

Clock Subtree After Cloning

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Harish Dangat

Comparing Single Pass and Two pass flow

place_opt clock_opt place_opt clock_clone new place_opt clock_opt

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Harish Dangat

Different schemes to minimize latency

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Harish Dangat

Conclusion

  • Clock gating is requirement for low-power

design

  • Closing CE timing requires to pay attention at all

stages of design

  • By planning at every step, CE timing can be

closed in high-speed low-power designs

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Harish Dangat

Thank You !

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Harish Dangat

BACKUP SLIDES

BACKUP SLIDES

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Harish Dangat

Battery Life is Important

http://www.phonesreview.co.uk/2012/09/26/iphone-5-vs-samsung-galaxy-s3-battery-life-confrontation/

Smartphone power for continuous web access

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Harish Dangat

  • Use process designed for low power
  • Use low power architecture
  • User power-gating
  • Use Clock-gating

How to Minimize Power

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Harish Dangat

Power Saving Opportunity

Clock Gating

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Harish Dangat

  • 20% to 40% Dynamic power is consumed by

clock tree

  • About 80% clock tree power is consumed last

stages of clock tree

Few Facts About Clock Tree Power

Ref – ISPLED, 2008

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Harish Dangat

Architectural/Corse Grain Clock Gating

USB-0 USB-1 Control Logic

Clock_EN Clock_EN USB_CLOCK

en_usb_0 en_usb_1

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Harish Dangat

Automated/Fine Grain Clock Gating

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Harish Dangat

Example of Automated/Fine Grain Clock Gating

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Harish Dangat

What To Look For In ICG

  • Too many flops used for

generating CE signal

  • Large delay in combinational path
  • Generating flops placed away

from ICG cells

  • Flops used to generated ICG

signal placed away from each

  • ther
  • Too man flops receive gated clock

Flops receiving gated clock Flops generating gated clock Comb cells in clock gating path

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SLIDE 39

39

Harish Dangat

What To Look For In ICG

  • Too many flops used for

generating CE signal

  • Large delay in combinational path
  • Generating flops placed away

from ICG cells

  • Flops used to generated ICG

signal placed away from each

  • ther
  • Too man flops receive gated clock

Flops receiving gated clock Flops generating gated clock Comb cells in clock gating path

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SLIDE 40

40

Harish Dangat

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41

Harish Dangat

What To Look For In ICG

  • Too many flops used for

generating CE signal

  • Large delay in combinational path
  • Generating flops placed away

from ICG cells

  • Flops used to generated ICG

signal placed away from each

  • ther
  • Too man flops receive gated clock

Flops receiving gated clock Flops generating gated clock Comb cells in clock gating path