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TIMING CLOSURE TIMING CLOSURE FOR FOR ULTRA DEEP SUBMICRON ULTRA DEEP SUBMICRON DESIGN DESIGN ASP-DAC 2001, Yokohama Tutorial 3 Presenters: Presenters: Jason Cong - - University of California, Los Angeles University of California, Los

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TIMING CLOSURE TIMING CLOSURE FOR FOR ULTRA DEEP SUBMICRON ULTRA DEEP SUBMICRON DESIGN DESIGN

ASP-DAC 2001, Yokohama Tutorial 3

Presenters: Presenters:

Jason Cong Jason Cong -

University of California, Los Angeles

University of California, Los Angeles Olivier Olivier Coudert Coudert -

Monterey Design Systems

Monterey Design Systems Patrick Patrick Groeneveld Groeneveld -

Magma Design Automation

Magma Design Automation Lou Lou Scheffer Scheffer – – Cadence Design Systems Cadence Design Systems

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ASP-DAC'01 Tutorial 3 Timing closure for UDSM design I-2

Tutorial Outline

I I Part I: Introduction (Jason Cong)

Part I: Introduction (Jason Cong)

I I Part II: Timing closure today (Lou

Part II: Timing closure today (Lou Scheffer Scheffer) )

I I Part III: Gain

Part III: Gain-

based synthesis (Patrick

based synthesis (Patrick Groeneveld Groeneveld) )

I I Part IV: Physical design closure (Olivier

Part IV: Physical design closure (Olivier Coudert Coudert) )

I I Part V: New approaches to harness global

Part V: New approaches to harness global interconnects (Jason Cong) interconnects (Jason Cong)

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ASP-DAC'01 Tutorial 3 Timing closure for UDSM design I-3

Tutorial Schedule

09:30am: Introduction (Jason Cong) 09:30am: Introduction (Jason Cong)

09:40am: Timing closure today (Lou 09:40am: Timing closure today (Lou Scheffer Scheffer) )

10:50am Break 10:50am Break

11:10am: Gain 11:10am: Gain-

based synthesis (Patrick

based synthesis (Patrick Groeneveld Groeneveld) )

12:30pm: Lunch 12:30pm: Lunch

02:00pm: The Quest for design closure (Olivier 02:00pm: The Quest for design closure (Olivier Coudert Coudert) )

03:20pm: Coffee Break 03:20pm: Coffee Break

03:40pm: New approaches to harness global interconnects (Jason 03:40pm: New approaches to harness global interconnects (Jason Cong) Cong)

05:00pm: Wrap 05:00pm: Wrap-

up and conclusions

up and conclusions

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ASP-DAC'01 Tutorial 3 Timing closure for UDSM design I-4

Technology (um) 0.25 0.18 0.15 0.13 0.10 0.07 Year 1997 1999 2001 2003 2006 2009 # transistors 11M 21M 40M 76M 200M 520M On-Chip Clock (MHz) 750 1200 1400 1600 2000 2500 Area (mm2) 300 340 385 430 520 620 Wiring Levels 6 6-7 7 7 7-8 8-9

Exponential Growth of Chip Capacity

Moore’s Moore’s Law Law

N Min. transistor feature size decreases by 0.7X every three years

Min. transistor feature size decreases by 0.7X every three years

N True for at least 30 years! (first published in April 1965)

True for at least 30 years! (first published in April 1965)

1997 National Technology Roadmap for Semiconductors 1997 National Technology Roadmap for Semiconductors

I I Enables system

Enables system-

a-

chip integration

chip integration

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ASP-DAC'01 Tutorial 3 Timing closure for UDSM design I-5

Productivity Gap

Where Moore Law May Break

x x x x x x x

21%/Yr. Productivity growth rate

58%/Yr. Complexity growth rate

1 10 100 1,000 10,000 100,000 1,000,000 10,000,000

1998

10 100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000

Logic Transistors/Chip (K) Transistor/Staff-Month

Chip Capacity and Designer Productivity

2003 Source: NTRS’97

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ASP-DAC'01 Tutorial 3 Timing closure for UDSM design I-6

Approaches to Increase Design Productivity

I I Raise level of design abstraction

Raise level of design abstraction

I I Use hierarchical design

Use hierarchical design Both require synthesis and layout timing closure Both require synthesis and layout timing closure

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ASP-DAC'01 Tutorial 3 Timing closure for UDSM design I-7

Levels of Abstraction in VLSI Design

Behavior-level Synthesis Hardware Description Language Logic-level Synthesis Boolean Equations/Networks Physical-level Design Billions of Rectangles

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ASP-DAC'01 Tutorial 3 Timing closure for UDSM design I-8

Difficulties in Maintaining High-Level Abstraction & Hierarchical Design

I I Interconnect delay far dominates device delay

Interconnect delay far dominates device delay

N N Can no longer design in behavior/functional domain

Can no longer design in behavior/functional domain

Technology (um) 0.25 0.18 0.15 0.13 0.10 0.07

Intrinsic gate delay (ns) 0.071 0.051 0.049 0.045 0.039 0.022

1mm (ns)

0.059 0.049 0.051 0.044 0.052 0.042

2cm no-opt (ns)

2.589 2.48 2.65 2.62 3.73 4.67

2cm best-opt (ns)

0.895 0.793 0.77 0.7 0.77 0.672

Best-opt uses simultaneous buffer insertion, driver/buffer sizing, and wiresizing
Reverse scaling of higher metal layers were not considered
Source: [Cong97] SRC Working Papers http://www.src.org/research/frontier.dgw

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ASP-DAC'01 Tutorial 3 Timing closure for UDSM design I-9

Difficulties in Maintaining High-Level Abstraction & Hierarchical Design

I I Current design hierarchy is based on

Current design hierarchy is based on functionality functionality

N N interconnect delay

interconnect delay

N N crosstalk

crosstalk

N N P/G bounce due to simultaneous switching, etc …

P/G bounce due to simultaneous switching, etc … => do not fit naturally into function hierarchy => do not fit naturally into function hierarchy

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ASP-DAC'01 Tutorial 3 Timing closure for UDSM design I-10

Coupling Noise Problem

0.000 0.050 0.100 0.150 0.200 0.250 0.300 0.350 250 180 150 100 70

Technology (nm) Noise / Vdd

a pair of in-phase aggressors

ne aggressor

a pair of skewed

Coupling noise from two adjacent aggressors to the middle victim wire (1 mm) with 2x min. spacing. Rise time is 10% of projected clock period.

Coupling noise depends strongly on both spatial and temporal relations!

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ASP-DAC'01 Tutorial 3 Timing closure for UDSM design I-11