A/D Conversion and A/D Conversion Filtering for Ultra Low - - PowerPoint PPT Presentation

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A/D Conversion and Filtering for Ultra Low

Advanced Digital IC Design

Filtering for Ultra Low Power Radios Dejan Radjen

Low Power Circuits, Dejan and Yasser, 2012-02-14 1

Dejan Radjen Yasser Sherazi

Contents

A/D Conversion

A/D Converters Introduction Oversampling A/D Converters ΔΣ modulator for Ultra Low Power Radios Measurement Results

Sub-VT Digital Circuits

Motivation and Sub-VT Basics

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High-level Modeling in the Sub-VT Domain Energy-Throughput Analysis w.r.t. different VT’s Reliability Analysis Conclusions

Why is this important?

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A/D Conversion

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A/D converters introduction

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A/D converters introduction

White noise approximation accuracy

Accurate for rapidly changing and random input signals Increases with the number of bits in the quantizer Increases with the number of bits in the quantizer Least accurate for 1-bit quantizers but used anyway

Maximum theoretical SNR for an N-bit ideal ADC

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6.02 1.76 = +

dB

SQNR N

Oversampling A/D Converters

Basic principle of oversampling

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Oversampling A/D Converters

Basic principle of oversampling

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Oversampling A/D Converters

ΔΣ modulation for A/D conversion

General ΔΣ-modulator Linear model

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( ) ( ) ( ) ( ) ( ) = + Y z STF z X z NTF z E z ( ) STF z ( ) NTF z

Signal Transfer Function: Noise Transfer Function:

Oversampling A/D Converters

SQNR controlled by

Order of the loop filter Number of bits in the quantizer Number of bits in the quantizer Oversampling ratio

ΔΣ ADCs vs. Nyquist ADCs

+ High resolution obtained with few bits in the quantizer + Mismatch in the quantizer suppressed by the loop

• Additional analog blocks in the loop filter

Feedback loop stability issues

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• Feedback loop → stability issues

Oversampling A/D Converters

Continuous Time ΔΣ-modulators

Continuous time Discrete time

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Sampling operation moved after the loop filter Implicit anti alias filtering inherited

domain domain

Ultra Low Power Receiver

Synchronization RF front end ΔΣ modulator Decimation filters Matching filters Analog decoder Digital Baseband Specifications Supply voltage: 900 mV

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Supply voltage: 900 mV Maximum input signal: 200 mV diff Power consumption: 300 μW Bandwidth: 125 kHz SNDR target: 70 dB Sampling frequency: 4 MHz

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CT Modulator for ULP Radios

A third order, 3-bit CT ΔΣ modulator has been implemented in CMOS

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[1] D. Radjen, P. Andreani, M. Anderson and L. Sundström, “A Low Power Continuous Time ΔΣ Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback ,” Norchip, Nov. 2011.

DAC mismatch

In multi-bit DACs, mismatch between DAC cells causes nonlinearities cells causes nonlinearities Digital correction techniques are used to correct for mismatch One successful correction technique is called Data Weighted Averaging (DWA)

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ata e g ted e ag g ( )

DWA algorithm

Implementation of the DWA algorithm

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Layout

Loop filter Flash ADC DWA Output buffers Decoupling capacitors

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DAC1 DAC2 DAC3

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Measurement Results

Results summary

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Chip photo

Measurement Results

Output spectrum

HD2=-73dBFS HD3=-73dBFS

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DWA on DWA off

Measurement Results

SNR/SNDR vs. amplitude

Peak SNDR=70 dB @ -2.5 dBFS Peak SNR=74 dB @ 1 7 dBFS

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@ -1.7 dBFS

Conclusions

ΔΣ modulators achieve high resolution using a few bits in the quantizer few bits in the quantizer Multi-bit CT ΔΣ are sensitive to errors in the feedback DAC – Digital correction needed ΔΣ modulation Usually employed for moderate resolution but pushing towards higher

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eso ut o but pus g to a ds g e resolutions and higher frequencies

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Sub-VT Digital Circuits

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Motivation and Sub-VT Basics

• Energy minimum
• perating voltage in

sub-VT. sub VT.

• Circuit operates at

critical path speed, idle time is minimized.

• Delay increases

exponentially.

Energy Optimum Region

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p y

Main Sources of Leakage

Gate leakage

Tunneling of electrons from bulk and the

GATE BTBT BTBT SUB

from bulk and the

• verlapped p-n

diffusion region into the gate through the thin oxide.

P-N junction leakage

Flow of the minority

BULK

Sub-threshold leakage

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y carries drifting from the reverse p-n junction between both source and drain to bulk (BTBT). Caused by diffusion of carriers in weak inversion region.

Normalized average leakage in Inverter Circuitry using RBB

At VDD =0.1V, we get 6% leakage reduction. At VDD = 0.3V, we get 16% leakage reduction. At V = 1 2V we get

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At VDD = 1.2V, we get 20% leakage reduction.

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High‐level Modeling in the Sub‐VT Domain [1]

No standard/commercial flow available which simply characterizes designs with VDD ≤ 400 mV. High‐level Energy Model

Conventional EDA tools. SPICE‐accurate in a fraction of SPICE simulation time. Any RTL design. Standard‐ and full‐custom based designs.

Script Based Processing

Good For Initial Charaterization Low Power Circuits, Dejan and Yasser, 2012-02-14 25

[1] O. Akgun, J. Rodrigues, Y. Leblebici, and V. Owall, “High‐level energy estimation in the sub‐VT domain: Simulation and measurement of a cardiac event detector,” in IEEE TBIOCAS. [2] Pascal Meinerzhagen, Oskar Andersson, Yasser Sherazi, Andreas Burg, and Joachim Rodrigues, ” Synthesis Strategies for Sub‐VT Systems” ECCTD 2011.

Good For Initial Charaterization For Sign‐Off, recharaterized Sub‐VT lib flow is used to get better timing information [2]

Energy Model Application Effect of Switching Activity on EMV [3]

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High switch activity shifts EMV to lower voltages. Sub optimal operational frequency leads to high energy dissipation.

[3] Oskar Andersson, S. M. Yasser Sherazi, and Joachim N. Rodrigues, “Impact of Switching Activity on the Energy Minimum Voltage for 65 nm Sub‐VT CMOS”. Submitted

Energy Model Application

• Decimation Filter Chain [4,5]

Requirements

Minimum energy per sample operation. D i d f 8 M l / 0 25 M l /

Original

Decimate data from 8‐Msamples/s to 0.25‐Msamples/s.

Questions:

Optimal operational voltages. Architectures that provide sufficient throughputs need to be developed. Selection of cells based on threshold options in 65‐nm.

• Various architectures of a half band digital filter (HBD)

i l d

Parallelized by 4

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are implemented:

Parallelized by 2,4, and 8. [4] S. Sherazi, J. Rodrigues, O. Akgun, H. Sjöland, and P. Nilsson, “Ultra low power sub‐VT decimation filter chain,” Norchip, 2010. [5] S. Sherazi, P. Nilsson, O. Akgun, H. Sjöland, and J. Rodrigues, “Design exploration of a 65 nm sub‐VT CMOS digital decimation filter chain,” ISCAS, 2011.

Energy‐Throughput Analysis w.r.t. different VT’s

Minimum Energy Throughput @ 250‐mV

• Energy vs VDD.

HVT cells have least energy dissipation.

Energy vs Throughput.

SVT cells have least energy dissipation Low Power Circuits, Dejan and Yasser, 2012-02-14 28

HVT cells have least energy dissipation.

SVT cells have least energy dissipation for moderate throughput requirments. HVT = High VT Cells SVT = Standard VT Cells LVT = Low VT Cells

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Dual‐VT Implementations [5]

Minimum Energy Throughput @ 250‐mV

E V lt

H+S SVT HVT H+S SVT HVT

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Energy vs Voltage

No advantage is observed for H+S combination.

[5] S. Sherazi, Joachim N. Rodrigues, Omer C. Akgun, Henrik Sjöland, and Peter Nilsson“Ultra Low Energy Design Exploration

• f Digital Decimation Filters in 65 nm Dual‐VT CMOS in the Sub‐VT Domain”, MicroProcessor, Elsevier 2011 (Finial revision)

Standard‐Cell‐Based Memory [6]

• SRAM macro‐cells become

significantly larger due to the need for 8 T or 10 T [7] bit‐cells

Super‐VT or Nominal

for 8 T or 10 T [7] bit cells

• Additional assist circuits required

for reliable sub‐VT operation (sense‐amplifier).

p

T

Voltage

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• Latch arrays are smaller than SRAM macro‐cells for storage capacities of up to

around 1 kbit.

[6] N. Verma and A. Chandrakasan, “A 65nm 8‐10T sub‐VT SRAM employing sense‐amplifier redundancy,” in Proc. IEEE ISSCC, Feb. 2007. [7] P. Meinerzhagen, S. M. Y. Sherazi, A. Burg, and J. N. Rodrigues, “Benchmarking of standard‐cell based memories in the sub‐VT domain in 65‐nm CMOS technology,” IEEE Journal on JETCAS, 2011.

Standard Cell Based Memories (SCM) [7]

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Energy vs Voltage

Flip‐Flop based implementation are a bit faster.

[7] P. Meinerzhagen, S. M. Y. Sherazi, A. Burg, and J. N. Rodrigues, “Benchmarking of standard‐cell based memories in the sub‐ VT domain in 65‐nm cmos technology,” IEEE Journal on JETCAS, 2011.

Energy Analysis of SCMs

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Energy vs Voltage

Latch based multiplexer clock‐gate architecture for R = 256, C = 128 and for R = 128, C =

• 256. The Δ corresponds to [8], a hard macro SRAM memory.

[8] B. H. Calhoun and A. P. Chandrakasan, “A 256‐kb 65‐nm subthreshold SRAM design for ultra‐low‐ voltage operation,” in IEEE J. of Solid‐State Circuits, 2007.

9 Reliability Analysis

SNM

Eye diagram of the latch used in the SCM architecture for VDD=0.4V and VDD=0.25V.

SNM

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1000‐point Monte Carlo circuit simulation assuming within die process parameter variations. Operation is still possible below VT, but the SNMs are small and reliability starts to become critical at 250mV.

Conclusions

A high‐level energy flow for sub‐VT domain characterization was presented. Enables architectural design space exploration Enables architectural design space exploration. Dual‐VT implementations may not be beneficial. SCM are promising option for sub‐VT memories. Proper knowledge of input stimuli is crucial for system specification.

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p g p y p