Clock Synchronization Synchronization Clock Henrik Lnn - - PDF document

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Clock Synchronization Synchronization Clock Henrik Lnn - - PDF document

Parallel and Distributed Systems: Clock Synchronization Clock Synchronization Synchronization Clock Henrik Lnn Electronics & Software Volvo Technological Development VTD Electronics and Software Parallel and Distributed Systems: Clock


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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Clock Clock Synchronization Synchronization

Henrik Lönn Electronics & Software Volvo Technological Development

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Contents Contents

  • General
  • Types of Synchronisation
  • Faults and problems to cope with
  • Example algorithms
  • Transmission delays
  • Derivation of criterion n>3m
  • Derivation of clock precision
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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

ECU ECU

Why Why do do we we need need an an agreed agreed time? time?

  • Consistent inputs/outputs
  • Control loops
  • Rollback recovery
  • Time-triggered task execution
  • Resource utilization

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Clock Clock Synchronization Synchronization

  • Internal vs. External
  • Master-Slave vs. Distributed
  • Hardware vs. software
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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Synchronization Synchronization Goals Goals: :

  • High Precision -Small deviation, or

skew, between clocks

  • High Accuracy - Small deviation to

external time

  • Monotonic and “Continuous” time

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Clock drift Clock drift

  • Why should clock drift be small?

Generally: All users of the clock service require a certain accuracy & precision => Clock synchronization must be performed more

  • ften with large drift

( )(

)

( )(

)

d dt i

C t t t t t t − < − ≤ − ≤ − 1

2 1 2 1 2 1

ρ ρ ρ

  • r

1- 1+

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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

How How often

  • ften should

should we we re re-

  • synchronize

synchronize? ?

– ρ: A rate deviation from external time (s/s) – R: Time between synchronizations – ∆s: Precision after synchronization Skew increase by R*2ρ between two synchronizations ⇒ Choose R so that ∆s+R*2ρ < Req. precision

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

How How often

  • ften should

should we we re re-

  • synchronize

synchronize? ?

  • Loosely coupled systems:

– Inaccurate, expensive clock readings=> Use high accuracy clocks, synchronize seldom

  • Tightly coupled systems:

– Accurate clock readings=> Use low accuracy clocks and synchronize often (∆s+R*2ρ < Req. precision)

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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Rate Rate adjustment adjustment

  • Clock rate is adjusted

– Required adjustment: ∆ – Time between adjustments: R => Adjust rate with ∆/R

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Oscillators Oscillators

  • Inverters
  • RC oscillators 10-3
  • Quartz oscillators 10-6
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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Hardware Hardware clock clock synchronization synchronization

  • Use a “clock distribution network”

– Much hardware required – Very good precision

Collection

  • f Clock

readings

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Phase Phase Locked Loop Locked Loop

≈feedback control loop

Comparator Filter Oscillator (VCO) Vc φr φi

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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Full Full connectivity connectivity not not required required

A cluster is fully connected internally and connected to at least one clock in each cluster pi +M-1≥ 3m+1

“Number of Clock inputs > 3 times number of faults”

  • M number of clusters
  • pi clocks in cluster i
  • m faulty clocks are tolerated

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Software Software clock clock synchronisation synchronisation: :

  • Use messages

– Cheap in hardware – Flexible – Low precision

Current time is 1500

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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Hardware Hardware assisted assisted Software Software clock clock synchronisation synchronisation: :

  • Use messages whose exact point of

arrival is recorded by hardware

– Cheap in hardware – high precision on suitable topology

Current time is 1500 Beep! Exact arrival time is 15:01

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

CC: 1 ... CCmax 1 Message from node: 1 ... max 1 Communication Cycle, CC t t

Use Use of

  • f pre

pre-

  • scheduled

scheduled events as events as clock clock readings readings

TDMA: Time Division Multiple Access

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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Faults Faults

  • Excessive drift
  • Clock reading errors
  • Byzantine faults (“Dual-faced” clocks)

– The faulty clock gives different readings to different nodes

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Cliques Cliques

Clock groups that are mutually unsynchronized

– Clock synch. algorithm must prevent this!

This group follows clock B This group follows clock E Slowest A Slower B Slow C Fast D Faster E Fastest F

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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Byzantine Byzantine faults faults

  • Effect on a ”sensible” algorithm:

(Syncronize to median of clock readings):

“I’m Slower” “I’m Slow” “I’m Fast” “I’m Faster” Faulty Byzantine lie This group will follow clock B This group will follow clock D A C E D B I’m slowest I’m fastest C C

  • Solution: Use a fault tolerant algorithm.
  • 3m+1 clocks to tolerate m clock failures

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Convergence Convergence vs vs Consistency Consistency Algorithms Algorithms

  • Interactive convergence algorithms

– Adjustment function guarantees limited clock skew in spite of faulty clocks and different sets of clock readings

  • Interactive consistency algorithms

– Agreement algorithm guarantees that all sets of clock readings are identical. Adjustment function is “arbitrary”, take e.

  • g. median

The presented algorithms are of this type

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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Collection

  • f Clock

readings

Interactive Interactive convergence convergence algorithm algorithm (CA1) (CA1)

  • Collect clock readings
  • Replace values larger than max with

an arbitrary value smaller than max

  • Take average of clock readings

Local Clock External clock Modulo 2*max counter Who's first detector Dn Up Clock deviation (Twos complement)

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Fault Fault Tolerant Tolerant Average Average algorithm algorithm (CA2) (CA2)

  • Mean of clocks excluding t fastest and

t slowest

Readings from different clocks New clock value

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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Midpoint Midpoint algorithm algorithm

  • Mean of fastest and slowest excluding

t fastest and t slowest

Readings from different clocks New clock value

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Convergence Convergence Nonaveraging Nonaveraging Algorithm Algorithm (CNA) (CNA)

  • Resynchronization interval=R
  • At synchronization i:

– If clock reaches iR, send synchronization message – Adjust time to iR if synchronization message arrive in time, and relay message – Ignore synchronization messages that arrive too early or too late (adjustment i has been done)

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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Transmission Transmission delays delays: :

  • Hardware/Hybrid environment:

Speed of light 3 ns/m

  • Software environment:

(Bounded) Message delays

Time is now 15.00! Not more? I have to set back my clock! Transmission delay

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Reducing Reducing effects effects of

  • f message

message delay delay in in loosely loosely coupled coupled systems: systems:

  • Incoming messages receive a

timestamp by hardware

  • Before a message is relayed, its clock

value is increased by the time spent in the node

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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Probabilistic Probabilistic Clock Clock Synch Synch. .

Request sent, t0 Minimum message delay Reply arrives, t1 Stochastic, additional delay Minimum message delay Stochastic, additional delay Request sent, t0 Request arrives Reply arrives, t1 Reply sent, tr

Time is Cremote!

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Probabilistic Probabilistic Clock Clock Synch Synch. .

1) Request reference clock reading from master

  • Request sent at t0 and clock reading Cremote received at t1

2) Assume that reading instant is Clocal=(t0+t1)/2 and calculate clock deviation Clocal -Cremote Make multiple readings until t1-t0 < threshold

– Total delay=t1-t0 – Total stochastic delay, dstoch=(t1-t0) -2*dmin – t0+dmin< tr<t0+dmin+ dstoch – Choose midpoint => error<dstoch/2

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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Correctness Correctness Criteria Criteria

For all partitions G1 and G2 of correct clocks such that all clocks in G1 are faster than those in G2:

C1: If all clocks in G1 use a reference that is faster than all clocks in G2 then there must be at least one clock in G2 that uses a reference that is at least as fast as the slowest clock in G1 and vice versa C2: If a clock uses a reference from a faulty clock, there must be correct signals that are slower and faster than the reference.

  • i. e. Faulty clocks that are used as a reference must be sandwiched

between correct clocks

Slowest Slower Slow Fast Faster Fastest

G2 G1

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Tolerating Tolerating Byzantine Byzantine Faults Faults

  • Correctness criterion C1=>

(If "no clock in G1 use reference in G2" then "a clock in G2 must use ref. in G1")

(1) (2)

(If "no clock in G2 use reference in G1" then "a clock in G1 must use ref. in G2")

fp(i)(N,m): Number of the reference clock used by clock i

(Clock readings numbered "fastest first". There are N clocks and m Byz. faults)

If then

x G p x y G p y

f N m G m f N m G

∈ ∈

≤ + ≤

1 2

1 1

max min

( ) ( )

( , ) ( , ) If then

y G p y x G p x

f N m G f N m G m

∈ ∈

≥ + ≥ + +

2 1

1 1 1 1

min max

( ) ( )

( , ) ( , )

Slowest Slower Slow Fast Faster Fastest

G2 G1

A B x

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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Tolerating Tolerating Byzantine Byzantine Faults Faults

(2)-(1) ⇒ (3) Avoid faulty clocks (Criterion C2) ⇒ Substitute in (3) ⇒

N-m - (m+1) ≥ m; N ≥ 3m+1

x G p x x G p y

f N m N m f N m m

∈ ∈

≤ − ≥ +

1 2

1

max min

( ) ( )

( , ) ( , )

m m N f m N f

y p G y x p G x

≥ −

∈ ∈

) , ( ) , (

) ( 2 ) ( 1

min max

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Attainable Attainable precision, CA2 precision, CA2

Precision after synchronization: ∆s Clock precision: δ Reading error: ε Synchronization interval: R

∆s=mδ/(N-2m) + ε

δ= ∆s+2Rρ= mδ/(N-2m)+ε+2Rρ ⇒ δ=( ε+2Rρ) ((N-2m)/(N-3m))

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Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Attainable Attainable precision, CA2 precision, CA2

Include uncertainty in R and time when correction is applied ⇒

δ= ∆s+ρ∆s+2ρ(1+ρ)R= (mδ/(N-2m)+ε+2Rρ) (1+ρ)

⇒ δ=(1+ρ)(ε+2Rρ) ((N-2m)/(N-3m-mρ))

Parallel and Distributed Systems: Clock Synchronization

VTD Electronics and Software

Summary Summary

  • Reasons for clock synchronisation
  • Some problems to cope with
  • Types of clock synchronisaton
  • Example algorithms
  • Derivation of attainable clock precision

for one algorithm