Designers: Tang Tang, Qiwei Wang, Lei Wu Supervisor: Professor Paul - - PowerPoint PPT Presentation

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Designers: Tang Tang, Qiwei Wang, Lei Wu Supervisor: Professor Paul - - PowerPoint PPT Presentation

Designers: Tang Tang, Qiwei Wang, Lei Wu Supervisor: Professor Paul Chow Project Overview Snake Classical Game + Motion Detection Xilinx XUP Virtex II Pro Development Board Review of Project Goals Major Goals: Basic game rules


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SLIDE 1

Designers: Tang Tang, Qiwei Wang, Lei Wu Supervisor: Professor Paul Chow

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SLIDE 2

Project Overview

Classical Game + Motion Detection Snake Xilinx XUP Virtex II Pro Development Board

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SLIDE 3

Review of Project Goals

Major Goals:

 Basic game rules (Start – Score – Game Over)  Real-time detection and tracking of the beacon  Real-time projection of snake body  “Game Start” and “Game Over” screens  Maintaining an acceptable frame rate so that the game is playable

Optional Goals:

 Beacon location calibration  Video effects, including colour and shaping of objects on screen  Sound effects for events in game  Increasing game difficulty × Additional obstacles on screen for increased difficulty × Difficulty level selection menu at game start screen × Numerical displaying of scoring × Automatic pause/resume when beacon is not detected

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Proposed Block Diagram

Video Decoder Chip Video To Ram Video_Out (xps_tft) MicroBlaze Beacon Location Detector Memory Controller (MPMC) Memory (DDR) PLB Composite Video PLB BRAM data BRAM instr

LMB LMB

UART SVGA

Start/End Game

Custom Logic + Audio Codec Speaker

Legend Custom IP Existing IP

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SLIDE 5

Final Block Diagram

Video Decoder Chip Video To Ram Video_Out (xps_tft) MicroBlaze Beacon Location Detector Memory Controller Memory (DDR) PLB Composite Video PLB BRAM data BRAM instr

LMB LMB

SVGA

GPIO

Custom Logic + Audio Codec Speaker

Legend Custom IP Existing IP

PLB PLB UART (Debugging)

GPIO to push button

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SLIDE 6

Design Process

1) Group discussion on design requirements and system architecture 2) Partition the entire design into smaller pieces (System » Software + Hardwar » Individual blocks) 3) Specify interface for each interconnection between blocks 4) Assign blocks to individual members to work in parallel 5) Individual approach: test-driven iterative design 6) Integrating finished pieces together, testing on larger scale 7) If anything goes wrong, goes back to step 3) to check interfaces

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SLIDE 7

Difficulties

  • The EDA tools are outdated and buggy
  • Technical issues: PLB protocol; video initialization

code; out of BRAM

  • Catch up with delayed schedule
  • GUI and graphics are time consuming
  • Nature of digital design: slow compilation,

simulation for testing and debugging

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SLIDE 8

What We Learned

  • General approach to designing digital systems as a

group

  • Technical skills: EDA and other software, test-

driven design approach, etc.

  • Efficient time management is critical
  • Communication is important
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SLIDE 9

Acknowledgement

  • Professor Paul Chow
  • Ruediger Willenberg
  • All our fellow students!
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SLIDE 10

Demo & Questions

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SLIDE 11

Thank you!