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Goal and Outline IC designers : awareness of memory challenges isQED 2002 Memory designers : no surprises, hopefully! March 20, 2002, San Jose Dominance of embedded Memories Memory Design Challenges Tomorrows High-quality SoCs Require

SLIDE 1

21.03.2002 Slide 1 Ulf Schlichtmann

March 20, 2002, San Jose

Ulf Schlichtmann Senior Director Cells & Memories Infineon Technologies AG isQED 2002 „Tomorrows High-quality SoCs Require High-quality Embedded Memories Today“

21.03.2002 Slide 2 Ulf Schlichtmann

Goal and Outline

IC designers: awareness of memory challenges Memory designers: no surprises, hopefully! Dominance of embedded Memories Memory Design Challenges Manufacturability Reliability SoC Design Support

21.03.2002 Slide 3 Ulf Schlichtmann

If Memory Does not Dominate Your Design Today, It Will Very Soon

Manufacturing Cost (area, yield, wafer cost) Dynamic and leakage power consumption Performance UDSM effects (IR-drop, EM, leakage (gate!), well proximity, ...) Time-to-tapeout Time-to-volume

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% Die Area 1999 2002 2005 2008 2011 2014

SOC Contents (SIA ITRS)

New Logic Reused Logic Memory

21.03.2002 Slide 4 Ulf Schlichtmann

Maximum eSRAM content per IC at IFX

5 10 15 20 25 0.35µm 0.25µm 0.18µm 0.13µm (so far) eSRAM contents [Mbit]

SLIDE 2

21.03.2002 Slide 5 Ulf Schlichtmann

Complexity: 36.7 mil transistors 1.2 million logic gates Area: 94.8 mm2 (0.18µm C10N) SRAM: 4.6 Mbit (400 macros!!) DSP: 4 Oak‘s MIPS: 5000 MIPS(Oak) ++ + Trellis/Viterbi Clock domains: 11 independent clks ~ 200 dependent clocks Frequency: 150/120 MHz (2 PLL‘s)

8-Channels ADSL Chip

21.03.2002 Slide 6 Ulf Schlichtmann

IWORX: Interworking Controller for 3G Mobile Base Station

Application:

ATM Line Card Controller for “Next Generation (3G) Mobile Infrastructure (UMTS Base Stations)”

Package: BGA388 Process: 0.18 µm CMOS 6 Layer Metal (fat) Chip Area: 193.7 mm2 13.72 mm x 14.12 mm Transistors: ~ 80 Mio. Gate Count: ~ 2.250.000 (including TricoreTM) SRAM: 11 Mbit (140 macros) Test Concept: Full Scan Path 63 Chains x ~2000 FF MemoryBIST

21.03.2002 Slide 7 Ulf Schlichtmann

Embedded DRAM Networking Switch Chip

Complexity: 850k logic gates Area: 117 mm2 (0.20µm C9DD1) Memory: 16 Mbit DRAM (4 Macros) 460 k SRAM 59 Register Files (241k total) Frequency: 100 MHz (1 PLL)

4 Mbit DRAM 4 Mbit DRAM 4 Mbit DRAM 4 Mbit DRAM PLL Reg Files Customer Logic SRAMs 21.03.2002 Slide 8 Ulf Schlichtmann

Memory Landscape changed dramatically over the last 10 years

Mostly SRAM Types: SP, DP, ROM Memories on shrinkpath Few EDA models Verification on Silicon SRAM/ROM, eDRAM, 1T, NVM, .... => integrated on SoC SoC vs. SiP Varied types, e.g. RFs, CAMs, ... New design for each generation > 15 EDA models; very high accuracy UDSM: Leakage; IR drop; EM; X-talk Tight coop. Design <==> TD / Fab Silicon Qualification essential

1990 2002 Challenges

SLIDE 3

21.03.2002 Slide 9 Ulf Schlichtmann

A high-quality Embedded Memory ...

meets requirements specifications can be manufactured with high yield at low cost can be tested economically meets reliability criteria enables timely product design

21.03.2002 Slide 10 Ulf Schlichtmann

A high-quality Embedded Memory ...

meets requirements specifications

– area – performance – active power – standby power – correct and accurate EDA modeling – functionality

can be manufactured with high yield at low cost

can be manufactured with high yield at low cost

can be tested economically

can be tested economically

meets reliability criteria

meets reliability criteria

enables timely product design

enables timely product design

21.03.2002 Slide 11 Ulf Schlichtmann

UDSM Process Technologies result in major challenges

Gate Overdrive Diminishing

0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 1,4 1,0 0,8 0,6 0,35 0,25 0,18 0,13 0,1

Process Generation [µm] V o ltage [ V ] VDD Vth

Dramatically increasing junction leakage Gate leakage Relative manufacturing variations increasing Dominance of wiring delays

21.03.2002 Slide 12 Ulf Schlichtmann

Key Issues in Excellent Memory Design

Bit Cell

– As small as possible (DR waivers) – Tradeoff area / leakage / performance – Electrically robust – Tuned for the specific target fab – Running in high volume

Architecture

– Low Leakage / High Speed – Active Well / Virtual Rail – Global / Local Bitlines – Multi-Banking – Timing Control Circuitry – Compiler-Optimized – Redundancy

Macro Layout

– Power Routing: IR Drop, EM, Size Power-ring – Crosstalk – DfM rules (incl. DRC runsets)

Sense Amplifier

– Voltage / Current Sensing – Robustness analysis (sensitivity, MC) – Layout critical (matching)

SLIDE 4

21.03.2002 Slide 13 Ulf Schlichtmann

A high-quality Embedded Memory ...

meets requirements specifications

meets requirements specifications can be manufactured with high yield at low cost

can be tested economically

can be tested economically

meets reliability criteria

meets reliability criteria

enables timely product design

enables timely product design

21.03.2002 Slide 14 Ulf Schlichtmann

Component development

MemLib MemLib

Continuous quality improvement silicon- proven Productlike chip Platform Qualific. Regular reviews TD-TCs Shrunk macros Macro Qualific. Macros for qualification Macro TCs Test- chips

Library Verification on Silicon

Excellent Quality Assurance - escorting the entire Development

21.03.2002 Slide 15 Ulf Schlichtmann

Semi-Custom Test Chip: TCQ-P (Test Chip for Qualification of Platform)

Parts similar to product Parts similar to product Parts for low level analysis Parts for low level analysis

p1 p2 p3 p4 functionality power consumption timing p1 p2 p3 p4 functionality power consumption timing

+

Qualification - not just verification

21.03.2002 Slide 16 Ulf Schlichtmann

TCQP - Test Chip for Qualification of Platform

Hvt memories Rvt memories Lvt memories

dpsram8k32 dpsram8k32 spsram8k32 spsram8k32 Memory BIST Memory BIST

SLIDE 5

21.03.2002 Slide 17 Ulf Schlichtmann

Memories, Testchips Must be Designed for Analyzability

Probe Points Bitmap capabilities Programmable Timing Control (Read Margin) S/H Measurements possible etc. Rapid analysis and yield ramp-up depend on

– Robust design – Design-for-Analysis techniques – Tight Cooperation between Design, Manufacturing and Analysis

21.03.2002 Slide 18 Ulf Schlichtmann

Manufacturing: High Yield & Low Cost => Redundancy

Definition: Introduction of spare elements to increase the circuit yield after production at the expense of overhead in area, power consumption or performance.

MEMORY Yield

20% 30% 40% 50% 60% 70% 80% 90% 100% 0,5 1,0 2,0 4,0 6,0 8,0 10,0 12,0 Memory Size [Mbit] Y i e l d w/ redundancy w/o redundancy

Cost: NRE, Area, Repair & Retest Hard vs. Soft Redundancy: Fuses, NVM, Register storage

21.03.2002 Slide 19 Ulf Schlichtmann

Manufacturing: High Yield & Low Cost => Redundancy

Block Redundancy

+ Easy to implement + Bit- / Wordline fails – Very large area overhead – Single / Double Bit fails

Row / Column Redundancy

+ Transparent to designer + Low area overhead for large mems + Bit- / Wordline fails – Area overhead for small mems – Multiple Single / Double Bit fails – Compiler Integration non-trivial

Redundant IO IO, XDEC, Ctrl Mem Cells Redundant Cells

Red. XDEC

Fuse Bank

21.03.2002 Slide 20 Ulf Schlichtmann

Word-based Redundancy

Advantages:

+ Good yield improvement, low area overhead

128 kbit: 2.5% 256 kbit: 1.3% from 1 Mbit on: <1%

+ Flexible sizes + One wrapper can handle multiple memories

RAM Fuse Bank Redundancy logic Chip

Synthesizable RTL Laser Marker

RAM

Disadvantage:

– Not robust to specific fault patterns (word- / bitline faults)

RAM RAM RAM RAM

SLIDE 6

21.03.2002 Slide 21 Ulf Schlichtmann No redundancy 1 word 2 words 3 words 4 words 5 words 6 words 1 WL 2 WL 3 WL 4 WL 1 IO 1 WL + 1 IO 2 WL + 1 IO 3 WL+ 1 IO 4 WL+ 1 IO 256 k 1 M 4 M 16 M

20,00%
10,00%

0,00% 10,00% 20,00% 30,00% 40,00% 50,00%

Productivity Gain (8kx32 macros)

Choice of Redundancy Solutions Required for Overall Optimum

21.03.2002 Slide 22 Ulf Schlichtmann

A high-quality Embedded Memory ...

meets requirements specifications

meets requirements specifications

can be manufactured with high yield at low cost

can be manufactured with high yield at low cost can be tested economically

– BIST vs. Memory Tester – Test algorithm: coverage vs. effort – TDR functionality (Test, Diagnosis, Repair)

meets reliability criteria

meets reliability criteria

enables timely product design

enables timely product design

21.03.2002 Slide 23 Ulf Schlichtmann

A high-quality Embedded Memory ...

meets requirements specifications

meets requirements specifications

can be manufactured with high yield at low cost

can be manufactured with high yield at low cost

can be tested economically

can be tested economically meets reliability criteria

– Electromigration – Soft Error Rate (SER)

enables timely product design

enables timely product design

21.03.2002 Slide 24 Ulf Schlichtmann

Radiation induced Soft Error Rate in embedded SRAMs

1 FIT = 1 failure / 109 hours

DRAM Soft Error Rate

1 10 100 1000 10000 100000 1000000 1M 4M 16M 64M

DRAM Generation FIT/Mbit

SRAM Soft Error Rate

1 10 100 1000 10000 100000 0,25µ 0,18µ 0,15µ 0,13µ

Process Generation FIT/Mbit

SLIDE 7

21.03.2002 Slide 25 Ulf Schlichtmann

What is radiation induced SER ?

A soft error is a non-destructive error caused by alpha particles or cosmic rays Ionizing radiation generates a current peak ⇒ flips a bit without physical damage ⇒ significantly delays a signal Memories and logic circuits are effected, depending on critical charge

+ -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + --

I t

1 10 100 0,35µ 0,25µ 0,18µ 0,13µ

Process Generation Q c rit in fC

21.03.2002 Slide 26 Ulf Schlichtmann

Measures for Radiation Hard Systems

fault tolerant architectures system simulations increase of critical charge no dynamic logic parity bits / check sums error correction codes etc. low alpha packages low alpha solder bumps B11 enriched BPSG SOI etc.

21.03.2002 Slide 27 Ulf Schlichtmann 20 10 30 40 50 60 70 80 90 100

4 8 12 16 20

Logic Area (mm²) Mem (MBit) SRAM 1T „SRAM“ (ident. Wafer Cost) eDRAM eDRAM SRAM

Choice of Memory Technology Depends on Many Factors

E.g. 0.13µm

Wafer Yield License Cost NRE (memory; process) Test cost (Burn-In?) Performance Operating Conditions Memory Granularity Availability Additional Decision Factors

21.03.2002 Slide 28 Ulf Schlichtmann

Choice of Memory Technology Depends on Many Factors

20 10 30 40 50 60 70 80 90 100

4 8 12 16 20

Logic Area (mm²) Mem (MBit) SRAM 1T „SRAM“ eDRAM eDRAM SRAM E.g. 0.13µm

Wafer Yield License Cost NRE (memory; process) Test cost (Burn-In?) Performance Operating Conditions Memory Granularity Availability Additional Decision Factors

SLIDE 8

21.03.2002 Slide 29 Ulf Schlichtmann

Choice of Memory Technology Depends on Many Factors

Alternatives: SoC vs. SiP MCM Face-to-Face => Directly Utilize Yield Learning of Commodity DRAM manufacturing

20 10 30 40 50 60 70 80 90 100

4 8 12 16 20

Logic Area (mm²) Mem (MBit) SRAM 1T „SRAM“ eDRAM eDRAM SRAM E.g. 0.13µm

21.03.2002 Slide 30 Ulf Schlichtmann

A high-quality Embedded Memory ...

meets requirements specifications

meets requirements specifications

can be manufactured with high yield at low cost

can be manufactured with high yield at low cost

can be tested economically

can be tested economically

meets reliability criteria

meets reliability criteria enables timely product design

– memories tightly integrated into the design flow – information about tradeoffs rapidly available – limited number of updates – concise information about changes for updates (tech. parameters!)

21.03.2002 Slide 31 Ulf Schlichtmann

Verification of Library Views for Design Flow

Component development

MemLib MemLib

Excellent Quality Assurance - escorting the entire Development

Continuous quality improvement silicon- proven Productlike chip Platform Qualific. Regular reviews TD-TCs Shrunk Macros Macro Qualific. Macros for qualification Macro TCs Test- chips

Library Verification on Silicon

3 2 Q-Level 1 Discrete quality levels

Single library regression test Single cell in single tool test

Regular reviews

Multi ilbraries regression test 21.03.2002 Slide 32 Ulf Schlichtmann

Verification of Library Views for Design Flow

Component development

MemLib MemLib

Excellent Quality Assurance - escorting the entire Development

Automate your QA! Install a separate QA team! Ensure corner case coverage Replicate designer behavior Focus Topics:

– Timing accuracy w/in flow – Power accuracy w/in flow

3 2 Q-Level 1 Discrete quality levels

Single library regression test Single cell in single tool test

Regular reviews

Multi ilbraries regression test

SLIDE 9

21.03.2002 Slide 33 Ulf Schlichtmann

Memory Explorer

Fast generation of datasheets for evaluations Easy comparison of memory configurations

21.03.2002 Slide 34 Ulf Schlichtmann