Goal and Outline IC designers : awareness of memory challenges isQED - PowerPoint PPT Presentation

Goal and Outline IC designers : awareness of memory challenges isQED 2002 Memory designers : no surprises, hopefully! March 20, 2002, San Jose � Dominance of embedded Memories � Memory Design Challenges „ Tomorrows High-quality SoCs Require � Manufacturability High-quality Embedded Memories Today “ � Reliability � SoC Design Support Ulf Schlichtmann Senior Director Cells & Memories Infineon Technologies AG Ulf Schlichtmann Ulf Schlichtmann 21.03.2002 21.03.2002 Slide 1 Slide 2 If Memory Does not Dominate Your Design Today, It Will Very Soon Maximum eSRAM content per IC at IFX SOC Contents (SIA ITRS) New Logic Reused Logic eSRAM contents [Mbit] Die Area Memory 100% 90% 80% 25 70% 60% 50% 20 40% 30% 15 20% 10% 0% 1999 2002 2005 2008 2011 2014 10 � Manufacturing Cost (area, yield, wafer cost) 5 � Dynamic and leakage power consumption 0 � Performance 0.35µm 0.25µm 0.18µm 0.13µm � UDSM effects (IR-drop, EM, leakage (gate!), well proximity, ...) (so far) � Time-to-tapeout � Time-to-volume Ulf Schlichtmann Ulf Schlichtmann 21.03.2002 21.03.2002 Slide 3 Slide 4

IWORX: Interworking Controller for 3G Mobile Base Station 8-Channels ADSL Chip Application: ATM Line Card Controller for Complexity: 36.7 mil transistors “Next Generation (3G) Mobile Infrastructure (UMTS Base Stations)” 1.2 million logic gates Package: BGA388 94.8 mm 2 (0.18µm C10N) Area: Process: 0.18 µm CMOS SRAM: 4.6 Mbit (400 macros!!) 6 Layer Metal (fat) DSP: 4 Oak‘s Chip Area: 193.7 mm 2 MIPS: 5000 MIPS(Oak) ++ 13.72 mm x 14.12 mm + Trellis/Viterbi Transistors: ~ 80 Mio. Clock domains: 11 independent clks Gate Count: ~ 2.250.000 ~ 200 dependent clocks (including Tricore TM ) Frequency: 150/120 MHz (2 PLL‘s) SRAM: 11 Mbit (140 macros) Test Concept: Full Scan Path 63 Chains x ~2000 FF MemoryBIST Ulf Schlichtmann Ulf Schlichtmann 21.03.2002 21.03.2002 Slide 5 Slide 6 Memory Landscape changed dramatically over the last 10 years Embedded DRAM Networking Switch Chip � SRAM/ROM, eDRAM, 1T, NVM, .... Challenges => integrated on SoC � SoC vs. SiP � Varied types, e.g. RFs, CAMs, ... Complexity: 850k logic gates Reg Files � New design for each generation 117 mm 2 (0.20µm C9DD1) Area: Customer � > 15 EDA models; very high accuracy Logic Memory: 16 Mbit DRAM (4 Macros) � UDSM: Leakage; IR drop; EM; X-talk 460 k SRAM � Tight coop. Design <==> TD / Fab PLL � Silicon Qualification essential 59 Register Files DRAM 4 Mbit DRAM (241k total) 4 Mbit Frequency: 100 MHz (1 PLL) � Mostly SRAM SRAMs � Types: SP, DP, ROM DRAM DRAM 4 Mbit 4 Mbit � Memories on shrinkpath � Few EDA models � Verification on Silicon Ulf Schlichtmann Ulf Schlichtmann 1990 2002 21.03.2002 21.03.2002 Slide 7 Slide 8

A high-quality Embedded Memory ... A high-quality Embedded Memory ... � meets requirements specifications � meets requirements specifications � can be manufactured with high yield at low cost – area – performance � can be tested economically – active power � meets reliability criteria – standby power � enables timely product design – correct and accurate EDA modeling – functionality � � can be manufactured with high yield at low cost can be manufactured with high yield at low cost � can be tested economically � can be tested economically � � meets reliability criteria meets reliability criteria � enables timely product design � enables timely product design Ulf Schlichtmann Ulf Schlichtmann 21.03.2002 21.03.2002 Slide 9 Slide 10 UDSM Process Technologies result in major challenges Key Issues in Excellent Memory Design � Sense Amplifier Gate Overdrive Diminishing � Bit Cell – Voltage / Current Sensing – As small as possible (DR waivers) VDD Vth – Robustness analysis 5 – Tradeoff area / leakage / performance (sensitivity, MC) – Electrically robust 4,5 – Layout critical (matching) – Tuned for the specific target fab 4 – Running in high volume � Dramatically increasing 3,5 junction leakage 3 V o ltage [ V ] � Architecture � Gate leakage 2,5 – Low Leakage / High Speed � Relative manufacturing 2 – Active Well / Virtual Rail variations increasing 1,5 – Global / Local Bitlines � Dominance of wiring � Macro Layout 1 – Multi-Banking delays – Power Routing: IR Drop, EM, – Timing Control Circuitry 0,5 Size Power-ring – Compiler-Optimized 0 – Crosstalk 1,4 1,0 0,8 0,6 0,35 0,25 0,18 0,13 0,1 – Redundancy Ulf Schlichtmann Ulf Schlichtmann Process Generation [µm] – DfM rules (incl. DRC runsets) 21.03.2002 21.03.2002 Slide 11 Slide 12

A high-quality Embedded Memory ... Excellent Quality Assurance - escorting the entire Development � meets requirements specifications � meets requirements specifications � can be manufactured with high yield at low cost � can be tested economically � can be tested economically � meets reliability criteria � meets reliability criteria � enables timely product design � enables timely product design MemLib MemLib Component development silicon- Regular reviews proven improvement Test- Platform chips quality Qualific. Macro Continuous Qualific. Macro Productlike TCs Macros chip TD-TCs for qualification Library Verification on Silicon Ulf Schlichtmann Ulf Schlichtmann 21.03.2002 21.03.2002 Shrunk macros Slide 13 Slide 14 Semi-Custom Test Chip: TCQ-P (Test Chip for Qualification of Platform) TCQP - Test Chip for Qualification of Platform p1 p2 p3 p4 dpsram8k32 spsram8k32 dpsram8k32 spsram8k32 Hvt memories Lvt memories Parts similar to product Parts similar to product functionality timing power + consumption p1 p2 p3 p4 Parts for low level analysis Memory BIST Memory BIST Parts for low level analysis functionality timing power consumption Rvt memories Qualification - not just verification Ulf Schlichtmann Ulf Schlichtmann 21.03.2002 21.03.2002 Slide 15 Slide 16

Memories, Testchips Must be Designed for Analyzability Manufacturing: High Yield & Low Cost => Redundancy � Probe Points � Definition: Introduction of spare elements to increase the circuit yield after production at the expense of overhead in area, power � Bitmap capabilities consumption or performance. � Programmable Timing Control (Read Margin) MEMORY Yield � S/H Measurements possible w/ redundancy w/o redundancy 100% � etc. 90% 80% 70% � Rapid analysis and yield ramp-up depend on d l e 60% Y i – Robust design 50% – Design-for-Analysis techniques 40% 30% – Tight Cooperation between Design, Manufacturing and Analysis 20% 0,5 1,0 2,0 4,0 6,0 8,0 10,0 12,0 Memory Size [Mbit] � Cost: NRE, Area, Repair & Retest Ulf Schlichtmann Ulf Schlichtmann � Hard vs. Soft Redundancy: Fuses, NVM, Register storage 21.03.2002 21.03.2002 Slide 17 Slide 18 Manufacturing: High Yield & Low Cost => Redundancy Word-based Redundancy Redundant IO IO, XDEC, Ctrl Synthesizable RTL Laser Marker Redundancy logic RAM RAM RAM RAM RAM RAM Chip Fuse Bank Fuse Bank Mem Cells Red. XDEC Redundant Cells � Advantages: � Disadvantage: � Block Redundancy � Row / Column Redundancy + Good yield improvement, low area overhead – Not robust to specific fault + Easy to implement + Transparent to designer � 128 kbit: 2.5% patterns (word- / bitline faults) + Bit- / Wordline fails + Low area overhead for large mems � 256 kbit: 1.3% – Very large area overhead + Bit- / Wordline fails � from 1 Mbit on: <1% – Single / Double Bit fails – Area overhead for small mems + Flexible sizes – Multiple Single / Double Bit fails + One wrapper can handle multiple memories Ulf Schlichtmann Ulf Schlichtmann – Compiler Integration non-trivial 21.03.2002 21.03.2002 Slide 19 Slide 20

Choice of Redundancy Solutions Required for Overall Optimum A high-quality Embedded Memory ... Productivity Gain (8kx32 macros) � meets requirements specifications � meets requirements specifications � can be manufactured with high yield at low cost � can be manufactured with high yield at low cost 50,00% � can be tested economically 40,00% – BIST vs. Memory Tester 30,00% – Test algorithm: coverage vs. effort 20,00% – TDR functionality (Test, Diagnosis, Repair) 10,00% � meets reliability criteria � meets reliability criteria 0,00% � enables timely product design � enables timely product design -10,00% 16 M -20,00% 4 M No redundancy 1 word 2 words 3 words 4 words 1 M 5 words 6 words 1 WL 2 WL 3 WL 4 WL 256 k 1 IO 1 WL + 1 IO 2 WL + 1 IO 3 WL+ 1 IO 4 WL+ 1 IO Ulf Schlichtmann Ulf Schlichtmann 21.03.2002 21.03.2002 Slide 21 Slide 22 A high-quality Embedded Memory ... Radiation induced Soft Error Rate in embedded SRAMs � meets requirements specifications � meets requirements specifications DRAM Soft Error Rate � can be manufactured with high yield at low cost � can be manufactured with high yield at low cost 1000000 � can be tested economically � 100000 can be tested economically 10000 FIT/Mbit SRAM Soft Error Rate � meets reliability criteria 1000 100 – Electromigration 100000 10 10000 – Soft Error Rate (SER) 1 FIT/Mbit 1M 4M 16M 64M 1000 � enables timely product design � enables timely product design DRAM Generation 100 10 1 0,25µ 0,18µ 0,15µ 0,13µ 1 FIT = 1 failure / 10 9 hours Process Generation Ulf Schlichtmann Ulf Schlichtmann 21.03.2002 21.03.2002 Slide 23 Slide 24