Interconnects Outline Interconnect scaling issues Aluminum - - PDF document

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Interconnects Outline Interconnect scaling issues Aluminum - - PDF document

Interconnects Outline Interconnect scaling issues Aluminum technology Copper technology araswat tanford University EE311 / Al Interconnects 1 Properties of Interconnect Materials Material Thin film Melting resistivity point


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EE311 / Al Interconnects

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Outline

  • Interconnect scaling issues
  • Aluminum technology
  • Copper technology

Interconnects

EE311 / Al Interconnects

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Properties of Interconnect Materials

Metals Silicides Barriers Material Thin film resistivity (µ cm) Melting point (˚C) Cu 1.7-2.0 1084 Al 2.7-3.0 660 W 8-15 3410 PtSi 28-35 1229 TiSi2 13-16 1540 WSi2 30-70 2165 CoSi2 15-20 1326 NiSi 14-20 992 TiN 50-150 ~2950 Ti3 0W7 0 75-200 ~2200 N+ polysilicon 500-1000 1410

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EE311 / Al Interconnects

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  • SILICIDES - Short local interconnections which have to be exposed to high

temperatures and oxidizing ambients, e.g., polycide and salicide structures.

  • REFRACTORY METALS – Via plugs, future gate electrodes, local

interconnections which need very high electromigration resistance.

  • TiN, TiW – Barriers, glue layers, anti reflection coatings and short local

interconnections.

  • Al, Cu - for majority of the interconnects

Interconnect Architecture

EE311 / Al Interconnects

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Al has been used widely in the past and is still used  Low resistivity  Ease of deposition,  Dry etching  Does not contaminate Si  Ohmic contacts to Si but problem with shallow junctions  Excellent adhesion to dielectrics Problems with Al

  • Electromigration ⇒ lower life time
  • Hillocks ⇒ shorts between levels
  • Higher resistivity

Why Aluminum?

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Electromigration due to electron wind induced diffusion of Al through grain boundaries SEM of hillock and voids formation due to electromigration in an Al line Electromigration induced hillocks and voids

void

Hillock Void

Metal Metal Dielectric

Electromigration

EE311 / Al Interconnects

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Fscat Ffield +

E field

FTOTAL = FSCAT + FFIELD

qz r E

D = µ r

  • q *

kT D r E

=

J = r E = r E

  • D = Do e

kT Ea

D = J qZ * kT D0 e Ea kT MTF e Ea kT

MTF = A m Jn eEa kT Using Einstein’s relation current density is related to E field by Diffusivity is given by Therefore Meantime to failure is thus of the form of A phenomenological model for MTF is

γ is the duty factor M, n are constants

Electromigration Theory

Where qz* is effective ion charge

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EE311 / Al Interconnects

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  • Energy dissipated is increasing as performance improves
  • Average chip temperature is rising

Thermal Behavior in ICs

4 5 6 7 8 9 50 70 90 110 130 150 170 190

Technology Node [nm] Chip Area [cm2]

75 100 125 150 175

Maximum Power Dissipation [W]

Source: ITRS 1999 EE311 / Al Interconnects

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Temperature Current Density

MTF = A rmJ n exp Ea kT

  • r is duty cycle

J is current density Ea is activation energy T is temperature A, m, and n are materials related constants

Mean time to failure is

Parametric Dependencies of Electromigration

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EE311 / Al Interconnects

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Ref: Yi, et al., IEEE Trans. Electron Dev., April 1995

MTF = A rmJ n exp Ea kT

  • r = duty cycle

J =current density

EM Limited Device Integration Density EM Limited Interconnect Width

Electromigration-Induced Integration Limits

Better packing techniques will be needed in the future to minimize the chip temperature rise

EE311 / Al Interconnects

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Composition Materials

Electromigration: Material and Composition

Adding Cu to Al decreases its self diffusivity and thus increases resistance to electromigration Materials with higher activation energy have higher resistance to electromigration

Ea (eV) Temperature (K) Cumulative failure (%) Failure Time (hours)

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Electromigration: Grain Structure

Top view

  • For Al grain boundary diffusion DGB >> Ds or DL

(Ds = surface diffusion, DL = lattice diffusion)

  • In a bamboo structure grain boundary diffusion is

minimized

DGB DS DL

Near bamboo structure

Self Diffusion in Polycrystalline Materials

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Bamboo Structure

  • With sufficient grain boundary migration a "bamboo

structure" may develop

  • No grain boundary diffusion in the bamboo structure

Effect of Post Patterning Annealing on the Grain Structure of the Film.

Increasing time and/or temperature

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EE311 / Al Interconnects

13 tanford University araswat e- Spanning grain Spanning grain Polygranular cluster

A B

atomic flux cluster cluster electric current, J back flux from stress Tensile stress metal atom depletion Compressive stress metal atom accumulation spanning grain polygranular cluster

On an average the flux is uniform in a uniform grain size textured film. If the grain size is non uniform the flux will vary accordingly.

(stress)

to t1 t

ss

  • (t1)

L

comp. tensile

build up of stress within polygranular cluster with time due to electromigration

Microstructural Inhomogeneities and Stress Induced Electromigration

EE311 / Al Interconnects

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(stress)

to t1 t

ss

  • (t1)

L

comp. tensile

  • Eventually, a steady-state is approached where the forward flux is

equal to the backward flux due to stress.

  • A criterion for failure of an interconnect under electromigration

conditions could be if the steady-state stress is equal to or greater than some critical stress for plastic deformation, encapsulent rupture, large void formation, etc.

  • The maximum steady state stress would occur at x=0 or x=L

Build up of stress within polygranular cluster with time due to electromigration.

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  • For very large line width/grain size (w/d) values, no spanning grains are present. No

points of flux divergence are present and the time to failure is relatively high.

  • As w/d decreases, some spanning grains occur. This results in divergences in the flux,

causing stress to develop that can be greater than the critical stress for failure (with L > Lcrit for most or all of the polygranular clusters). The lines would fail and the median time to failure would decrease.

  • As w/d decreases more, more spanning grains are present, but the lengths of the

polygranular cluster regions between them are shorter, many of them shorter than Lcrit. The stresses that develop, which create the back fluxes and which in turn eventually stop the electromigration flux, are in many cases smaller than the critical stress.

  • For small enough values of w/d bamboo or near-bamboo structures are present. The

polygranular clusters are few, and for some lines, all the clusters are shorter than Lcrit and the lines will not fail by this mechanism. The MTTF thus increases dramatically.

e-

  • ss

L 1

crit

  • ss

L 2

crit ss crit ss crit EE311 / Al Interconnects

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Electromigration: Grain Texture

  • Empirical relationship (for Al & Al alloys)

MTF eµ

  • 2 log[ I(111)

I(200) ]

3

  • S. Vaidya et al., Thin Solid Films, Vol. 75, 253, 1981

10

3

10

4

10

5

10

6

10

7

1.8 1.9 2.0 2.1 2.2 2.3

Time-to-Failure (sec) 1/T (10-3/K)

(111) CVD Cu E

a = 0.86 eV

(200) CVD Cu E

a = 0.81 eV

213 238 263 188°C Ref: Ryu, Loke, Nogami and Wong, IEEE IRPS 1997.

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Structure

Layered Structures: Electromigration

Layering with Ti reduces Electromigration

Time (arbitrary units) C u m u l a t i v e f a i l u r e Al-Si Layered Al-Si/Ti

Improvements in layered films due to redundancy

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Mechanical properties of interconnect materials

Material Thermal expansion coefficient (1/˚C) Elastic modulus, Y/(1- ) (MPa) Hardness (kg/mm2) Melting point (˚C) Al (111) 23.1 x 10-6 1.143 x 105 19-22 660 Ti 8.41 x 10-6 1.699 x 105 81-143 1660 TiAl3 12.3 x 10-6

  • 660-750

1340 Si (100) 2.6 x 10-6 1.805 x 105

  • 1412

Si (111) 2.6 x 10-6 2.290 x 105

  • 1412

SiO2 0.55 x 10-6 0.83 x 105

  • ~1700
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Layering with Ti reduces hillock formation

Layered Al/Ti Homogeneous Al/Ti Pure Al Surface profile

Layered Structures: Hillocks

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Difference in the expansion coefficients of the film and substrate causes stress in the thin film. (a) Film as-deposited (stress free). (b) Expansion of the film and substrate with increasing temperature. (c) Biaxial forces compress the Al film to the substrate dimension

Stress due to Thermal Cycling

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Process Induced Stress

0 100 200 300 400 500 300 200 100

  • 100

Temperature (˚C) Stress (MPa) Pure Al 0.64 micron thick H e a t i n g C

  • l

i n g Plastic deformation Elastic deformation Silicon Aluminum (in Si) Si pulls inward on Al at interface, inducing compressive stress on Al. (in Al) Expansion of Al with respect to Si EE311 / Al Interconnects

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Stress Measurement

  • Es is Young’s modulus of the substrate,
  • vs is Poisson’s ratio for the substrate,
  • (Es/1-vs) is the biaxial modulus of the

substrate,

  • ts is the substrate thickness,
  • tf is the film thickness, and
  • Rf is the radius of curvature induced by

the film

= Es 1 s

  • ts

2

6t f Rf

Biaxial stress in the film

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EE311 / Al Interconnects

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Hillocks

Hillock formation due to compressive stress and diffusion along grain boundaries in an Al film.

Al Al Al ILD ILD

EE311 / Al Interconnects

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Current Aluminum Interconnect Technology

  • xide
  • 1. oxide deposition
  • 2. via etch

resist barrier W

  • 4. W & barrier polish
  • 3. barrier & W fill

Fabrication of Vias

W Plug 0.5 micron Oxide

Glue

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Current Aluminum Interconnect Technology

Fabrication of Lines

Ti / TiN Al(Cu) Ti

  • 5. metal stack deposition
  • 6. metal stack etch
  • 8. oxide polish
  • 7. oxide gapfill
  • xide

EE311 / Al Interconnects

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Current Aluminum Interconnect Technology

(Curtsey of Motorola)

Al(Cu) - Metal 1 Ti TiN TiN TiN Ti TiN Al(Cu) - Metal 2 Silicon TiSi2 TiN W W

N+

Oxide

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Low Dielectric Constant (Low-k) Materials

Oxide Derivatives

F-doped oxides (CVD) k = 3.3-3.9 C-doped oxides (SOG, CVD) k = 2.8-3.5 H-doped oxides (SOG) k = 2.5-3.3

Organics

Polyimides (spin-on) k = 3.0-4.0 Aromatic polymers (spin-on) k = 2.6-3.2 Vapor-deposited parylene; parylene-F k ~ 2.7; k ~ 2.3 F-doped amorphous carbon k = 2.3-2.8 Teflon/PTFE (spin-on) k = 1.9-2.1

Highly Porous Oxides

Xerogels k = 1.8-2.5 Air k = 1

EE311 / Al Interconnects

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Thermal Conductivity for Commonly Used Dielectrics

Dielectric Film Thermal Conductivity (mW/ cm°C) HDP CVD Oxide 12.0 PETEOS 11.5 HSQ 3.7 SOP 2.4 Polyimide 2.4

3550 70 130 180 100

1 2 3 4 0.2 0.4 0.6 0.8 1 1.2 Technology Node [nm] Dielectric Constant Thermal Conductivity [ W / mK ]

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Embedded Low-k Dielectric Approach

Why embed Low-k dielectric

  • nly between metal lines?

 Mechanical strength  Moisture absorption in low-k  Via poisoning/compatibility with conventional dry etch and clean-up processes  CMP compatibility  Ease of integration and cost  Thermal conductivity

V I A V I A MET MET LOW k MET MET LOW k SiO2 (k~4.2) SiO2 (k~4.2) SiO2 (k~4.2)

Source: Y. Nishi, TI EE311 / Al Interconnects

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Air-Gap Dielectrics

2.0 2.5 3.0 3.5 4.0 4.5 0.2 0.4 0.6 0.8 1 Line/Space (um) Keff Experimental Simulated

Keff vs. Feature Size Capacitance

Total Capacitance (pF) 6.0 9.0 12.0 15.0 18.0 21.0 24.0 1 10 30 50 70 90 99 Air-Gap Structure HDP Oxide Gapfill Cumulative Probability

Al SiO2 Al Air

  • Reduced capacitance between wires
  • Heat carried mostly by the vias
  • Electromogration reliability is better because of stress relexation

allowed by free space Electromigration