Modeling and Characterization of High Frequency Effects in ULSI - - PowerPoint PPT Presentation

1 CADENCE DESIGN SYSTEMS, INC.

Modeling and Characterization of High Frequency Effects in ULSI Interconnects

Narain Arora and Li Song

narain@cadence.com May 11, 2005

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• Interconnect High Frequency Effects
• Resistance effect
• Inductance effect
• Capacitance effect
• Characterization of High Frequency Effects
• RC Delay
• Crosstalk Noise
• Power/Ground Bounce
• Conclusions

Outline

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• Aggressive Scaling

Interconnect dominates IC performance

• Manufacturing Related Issues

– Electron scattering – CMP etc.

• High Frequency Effects

– Timing/Delay – Ringing/Reflection – Signal integrity/Crosstalk – Power/Ground bounce etc.

An Overview

Source: ITRS Roadmap 1999

9+ metal levels

wire Via Global Local 0.65 0.5 0.35 0.25 0.13 0.10 µ

0.18 0.18 Delay (ps) 45 40 35 30 25 20 15 10 5 Gate Delay Interconnect Delay Al + SiO2

Interconnect dominates gate delay Interconnect dominates gate delay

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Electron Scattering

( )

        − +               + − + − = l S U p 1 2 . 1 1 1 ln 2 3 1 3 1

3 2

α α α α ρ ρ

r r d l − = 1 α

U is the perimeter and S is the cross-section area of the wire

Resistivity increase due to surface and grain boundary scattering

• W. Steinhoegl et al., SISPAD 2003

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Wire inductance effects

– Ringing and overshoot - problematic for clocks since glitches can be

• bserved as transitions leading to

faulty switching – Increased delay – Inductive crosstalk and reflections of signals due to impedance mismatch – Switching noise due to voltage drops

• problematic for power distribution

network

Inductance Effects

L di dt

After M. Beattie and L. T. Pileggi, DAC 2001

32-bit bus lines, left most line is active Signal line Neighboring line

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Resistance (Skin) Effect

More pronounced skin effect at high frequencies Due to cladding

CMP fills

20 40 60 80 100 120 140 160 180 200 0.10 1.00 10.00 100.00 Frequency (GHz) Resistance Ohm/mm Co-planar Floating Parallel Lines Ground Crossing Lines Al Model Al Model

m m µ ρ ⋅ Ω = 33

m m µ ρ ⋅ Ω = 29

( ) ( )

δ δ ρ t w l R exp 1− =

δ: Skin Depth

Highly resistive cladding Cu Wire

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Skin Effect Modeling

• SPICE simulations with/without Skin Effect
• Skin effect influence both reflection and signal propagation

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Field Solver Simulation and Modeling

0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 0.10 1.00 10.00 100.00 f (GHz) Inductance nH/mm

Co-planar Floating Parallel Lines Ground Crossing Lines Fast Henry Simulation Full Wave Simulation

Coplanar GND Return Coplanar Metal Fill Return

CMP metal fills blocks provide current return loop at high frequencies

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20 40 60 80 100 120 140 160 180 200 0.10 1.00 10.00 100.00 f (GHz) Resistance (Ohm/mm) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 Inductance (nH/mm) Measurement Model-Ladder Model-Branch

SPICE Modeling

Co-planar Inductance Structure

Previous Ladder and Branch models can’t predict both R and L values well

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High Frequency Capacitance (Cu)

• Relatively constant at high frequencies (peaks are resonant peaks, the

resonant frequency is smaller for structure with high capacitance)

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.01 0.10 1.00 10.00 100.00 Frequency (GHz) Capacitance pF/mm co-planar structure floating parallel lines gounded crossing lines

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Interconnect High Frequency Effect Characterization

• Two ways of characterizing interconnects are :
• 1. Use the Field Solvers that are based on Maxwell’s equations (soft

validation). Inherent assumption is that process parameters that are input to the solver are correct (from silicon prospective).

• 2. Test chips fabricated on Silicon Wafers for a given technology,

measuring the RCL of those structures (Silicon validation). Though expensive and time consuming, it is the only way to do correct model validation.

• Characterization Techniques

– S Parameter Measurement – TDR Measurement – Ring Oscillator Technique

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45 MHz 50 GHz S11 S12

S Parameter Measurement

TSMC 90nm Cu CMOS process

• S parameters are measured on test

structures (HP 8510C network analyzer (50MHz-50GHz), (Short, Open, Load and Through) SOLT calibration on Cascade standard*

• Test Structure pads are de-

embedded and parasitic are corrected

• Propagation constant and

characteristic impedance are extracted from S parameters measured as shown in Figure

• Resistance and inductance are

extracted from the propagation constant and characteristic impedance Smith Chart of Co-planar structure #1

* See Cascade Microtech website: www.cmicro.com

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RLCG Extraction

G C R L

S parameter response from a transmission line Solving for propagation constant and characteristic impedance , ,

Telegrapher’s equation model

From Then

Eisenstadt, et. Al. IEEE Tran. Component, Hybrids and Manufacturing Tech. pp483-490, Vol. 15, No. 4 Aug., 1992

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Ring Oscillators

200 400 600 800 1000 1200 1400 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 length (mm) Resonat Frequency (MHz)

667 0.750 0.030 0.720 0.30 3.00 2400 RO f0 (MHz) RO Delay (ns) LC Delay (ns) RC Delay (ns) C(fF) L (nH) R (Ohm)

RC delay dominates for 0.14um wide Cu wire delays

For wire length 6mm: Enable Out Spectrum Analyzer f0

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RC Delays

0.145 0.077 0.044 0.026 0.030 RC delay (fs/µm) 0.063 0.044 0.033 0.023 0.013 jwL (/µm) 3000 2000 1500 1000 500 SoC Freq. (KHz) 0.080 0.095 0.093 0.083 0.122 C (fF/µm) 1.813 0.815 0.476 0.314 0.246 R (Ω/µm) 2.90 2.60 2.20 2.20 3.70 Resistivity (µΩ⋅cm) 2.70 2.90 3.10 3.60 4.00 Dielectric Constant 140 200 270 360 800 Dielectric Thickness 200 270 320 350 580 Metal Thickness 80 100 140 200 280 Width /Spacing 45 65 90 130 180 Process Node (nm)

RC delay decreased at 130nm node due to the introduction of Cu and low k material Inductance effect increases as operating frequency increases RC delay increases again as resistivity of Cu wire increases (cladding and electron scattering)

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Manhattan vs. X Architecture Routing

Preferred direction with optimization

Manhattan Metal 1 Metal 2 Metal 3 Metal 4 Metal 5

A B C

30% shorter

A Better Way

A C B

Chip Impact: 20% Less Interconnect 30% Fewer Vias

Lower cost and Higher performance

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X Architecture Layout

Pervasive use of diagonal wires A typical layout and SEM picture

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Power Grid effects on Inductance

• L increases for increasing

spacing because more flux is enclosed between the signal lines and the return path

• In a realistic test structure, L

becomes less dependent on the spacing to the intended return

• ground. Local lines and

capacitive coupling provide alternative return paths

• S. S. Wong et. al. Proc. IEEE ISQED, pp. 389-394, 2003

Manhattan Signal X Architecture Signal

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FastHenry Simulation - Self Inductance

Small variation for diagonal signal line

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.10 1.00 10.00 100.00 f (GHz) L (nH/mm) X Mesh Manhattan Signal X Signal 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0.10 1.00 10.00 100.00 f (GHz) L (nH/mm) X Signal Manhattan Signal Manhattan Mesh

Manhattan Power Grid X Architecture Power Grid

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Crosstalk

• Capacitive Crosstalk
• Inductive Crosstalk
• Total Crosstalk

dt dV d Z L c Z d V

s m c FE

        − = 2 1

v K V

NE NE =

      + = L L C C K

m c NE

4 1

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Inductive Impact at Clock Signal

• Clock carries multi-

gigahertz frequency signals with short rise/fall time

• Inductive effects

actually reduce rise time at near end, but increases clock skews

• Modeled as co-planar

wave guide (CPWG)

Distributed RC/RLC SPICE model, inductance is frequency dependent in the parallel model

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Inductive Impact on Bus Lines

• Simultaneous signal switch increase timing push-out
• Leading to inductive noise

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Power/Ground Bounce

• On-chip power/ground grid noise is the Vdd/Vss fluctuation

due to Ldi/dt

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Conclusion

• Accurate characterization of high frequency effect such as skin

effect, inductance impact on clock, buses and power/ground grid are essential in VLSI design.

• High frequency skin effects, inductance and capacitance effects

and their impacts on clock, bus and power grids are studied.

• Modeling of RC delay, crosstalk and power/ground bounce are

presented.

• RLC extraction and modeling in sub-90nm technologies with

consideration of manufacturing effects such as electron scattering in nanometer wires, high aspect ratio wires and CMP effects