Carbon Nanotube Interconnects? Carl V. Thompson 1,3 , Vladimir M. - - PowerPoint PPT Presentation

Carbon Nanotube Interconnects?

Carl V. Thompson1,3, Vladimir M. Stojanovic2,4, Fred Chen2,4 and Gilbert D. Nessim1,3

1 Materials Science and Engineering, 2 Electrical Engineering and Computer Science 3 Microsystems Technology Laboratory, 4 Research Laboratory of Electronics

M.I.T.

• Overview of structure, properties and growth.
• Electronic properties.
• CNTs in circuits.
• The case for MWCNT vias.

Structure of Single-Wall CNTs (SWCNTs)

1/3 metallic 2/3 non-metallic if n and m are random then

A.P. Graham et al (Infineon) Appl. Phys. A 80, 1141–1151 (2005)

Multi-Wall CNTs (MWCNTs)

Each wall conducts independently: 1/3 metallic 2/3 non-metallic if n and m for a given shell is random then

CNT Properties

Electrical:

• Ballistic conduction over distances of order 1 micron (~10-4 Ω·cm).

‘Metals’ with low resistivities, Semiconductors with high mobilities

• Conductivity a strong function of adsorbates or reactants.

Mechanical:

• High elastic modulus (high stiffness) (~1 to 5 TPa vs. ~0.2 for steel).
• Very high tensile strength (~10 to 100 GPa vs. ~1 for steel).

Thermal:

• High room temperature thermal conductivity (~2000W/mK vs.

~400W/mK for copper). Electrical Stability:

• Maximum current density ( 109 A/cm2 vs. <107 A/cm2 for Cu).

Chemical Stability:

• C binding energy in graphene ~12 eV vs. Cu at a Cu surface ~ 4eV

Growth of CNTS

vapor-solid- tube Catalyst Formation: Uncontrolled dewetting of catalyst thin films.

Chhowalla et al (Cambridge U), J.Appl. Phys. 90, 5315 (2001).

Fundamental Assembly Methods

Grow - In - Place Grow - Then - Place

• Chemically-directed
• Field-directed
• Mechanically-directed

However, for MWCNTs

• nly the outer wall is contacted

so only the conductivity of the

• uter wall is measured

More relevant measurements are made for MWCNTs with metal contacts to all walls

• grow MWCNTs on metal; open
• ther end for ohmic contact.

Conductance measurements for SWCNT and MWCNTs are usually made by deposition of metal on top of horizontal tubes.

CNT Contact: SWCNTs vs. MWCNTs

• Y. Awano, IEICE Trans. Electron. E89–C,

1499 (2006); AMC 2006

Fujitsu Program: MWCNT Bundle-filled Vias

• 2μm-diameter vias
• Cu lines, CNT vias
• Deposition temperatures ~500C

with hot-filament CVD

• CNT densities up to 9 x 1011 cm-2

with Co nanoparticles on TiN/Ta/Cu

Kondo, MRS

c Q M K Q ES c Q

Equivalent Circuit Model for a SWCNT

LM = magnetic impedance LK = kinetic impedance ~16nH/μm LK >> LM CES = electrostatic capacitance CQ = quantum capacitance ~ 100aF/μm CQ ~ CES

P.J. Burke, IEEE Trans. on Nanotech. 1, 129 (2002)

c Q M K Q ES c Q

Equivalent Circuit Model for a SWCNT

C Q

R L 1 R R + ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + = λ

RC = contact resistance L = length λ = electron mean free path ~ 1μm RQ = quantum resistance

Ω k 5 . 6 ~ e N 2 h

2 chan

=

Nchan = number of channels = 2 when diameter < 6nm

(h = Planck’s constant, e = electronic charge)

Bundles of Single-Wall CNTs in Trenches

Factors Affecting Resistance:

• radius r
• spacing s
• mean free path λ
• length L
• fraction metallic fmet
• contact resistance RC

RC + (RQ/2) RC + (RQ/2) RL 1 2 n i tubes met N 1 i met

R N f R 1 f R 1

tubes

≈ =

∑

C Q i

R 2 L 1 R R + ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + = λ

2 2

s 3 2 cm # = ρ hw ~ Ntubes ρ

2 max

r 3 2 1 = ρ

2 14 max

cm 10 x 7 ~ nm 5 . r ρ ⇒ =

Bundles of Single-Wall CNTs in Trenches

fmet =.33 r = 0.5nm ρ = ρmax

Bundles of Single-Wall CNTs in Trenches

• A. Naeemi and J.D. Meindl,

IEEE Trans. on Electron

• Dev. 54, 26 (2007)

SWCNT bundles ‘win’ when L > 1μm Issue: no one knows a way to fill trenches at anywhere near the maximum density.

SWCNT Bundles in Vias

Factors Affecting Resistance:

• radius r
• density ρ (#/cm2)
• mean free path λ
• length L
• fraction metallic fmet
• contact resistance RC

Results similar to trenches: for ρ = ρmax RC = 0 Rvia,SWCNT ~ RCu when L > 1μm But ρmax = 7 x 1014 cm2 Fujitsu: ρ ~ 1012 cm2 (for rvia = 2μm)

One MWCNT per pore in an ordered porous alumina scaffold

Krishnan, Nguyen, Thompson, Choi, and Foo, Nanotechnology 16, 841 (2005).

Multi-Wall CNT Vias

• one MWCNT per pore grown on

metallic underlayer for multi-wall contact

• CMP or ion milling to trim and
• pen MWCNT
• deposit metal on opened MWCNT

for multi-wall contact

C Q i

R 2 L 1 R R + ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + = λ Ω k N 13 e N 2 h R

ch 2 ch Q

= = 275 . 1 r 3672 . ) r ( g 2 ) r ( g

S S S

+ = = rS < 1.5nm rS > 1.5nm Nch/shell = g(rS)*

*Naeemi and Meindl, IEEE Electron Device Letters 27, 338 (2006)

s = shell spacing ~ 0.34nm ri = inner shell radius ro = outer shell radius

Resistance of Multi-Wall CNTs

resistance of shell i with radius rs s r r N

i

• shells

− =

metallic N 1 i

f R 1 R 1

shells

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ =

∑

fmetallic = metallic fraction

ri

ro s

0.35kΩ 16nm 0.11kΩ 22nm Cu 25kΩ 16nm 16.7kΩ 22nm SWCNTs 2.25kΩ 16nm 1.47kΩ 22nm MWCNT Resistance Node

fmet = 0.33 L < λ RC = 5kΩ ri = rSWCNT = 0.5nm SWCNT: ρ = 1 x 1012 cm2

for ρ = ρmax RSWCNT,bundle < RMWCNT however, for ρ = 1012 cm2 RSWCNT,bundle > RMWCNT but RCu < RMWCNT < RSWCNT So why use CNTs?

• High reliability ( > 109 A/cm2 )
• Chemically stable (no liner required)
• Can fill high-aspect-ratio vias ( > 1000 to 1 in 10nm pores)

Resistance isn’t everything.

Intel 386 Intel 486 Intel Pentium

A System Perspective

Chip design used to be constrained only by delay. Each process generation would result in larger and/or more complex designs with more transistors running faster.

Intel Core 2 Duo AMD Quad Core Opteron

System Constraints Today

• At advanced process nodes:

Increased relative wire delay - can’t scale frequency Leakage No Voltage Scaling Increase in power density

• Designers utilize parallelism to improve performance,

but still limited by power constraint

• Multiple cores require communication between cores

System Constraints Tomorrow

uP uP uP uP

• Multiple cores require communication between cores
• To keep increasing performance…

System Constraints Tomorrow

• Multiple cores require communication between cores
• To keep increasing performance… we want to increase the number of

smaller & more efficient cores

• Increases burden on network - still power constrained

System Constraints Tomorrow

Modeling the Network

• Each connection in the network can be modeled as an inverter

driving a wire and a load, or some multiple of that for repeated wires.

• F. Chen, A. Joshi, V. Stojanović and A. Chandrakasan, Nanonets Symposium 07

CDRV = driver capacitance RDRV = driver resistance RW = wire resistance CW = wire capacitance CLOAD = load capacitance P = pitch S = spacing (within layer) H = interlevel spacing CC = fringing capacitance (coupling within layer) CP = plate capacitance (coupling between layers)

Re-Engineering the Wires

0.5 1 1.5 2 2.5 0.5 1 1.5 2 RW, normalized to nominal RW(Cu) CW, normalized to nominal CW(Cu) at 22 nm 1 0.8 1.5 2 0.6 0.4

CW/CW(Cu 22nm node) RW/RW(Cu 22nm node)

Nominal Cu case 22nm node L = 256μm Fanout = 1

Look at changing the interconnect stack and wire properties to improve performance and energy Normalized Delay Contours

Re-Engineering the Wires

0.5 1 1.5 2 2.5 0.5 1 1.5 2 RW, normalized to nominal RW(Cu) CW, normalized to nominal CW(Cu) at 22 nm 1 0.8 1.5 2 0.6 0.4

CW/CW(Cu 22nm node) RW/RW(Cu 22nm node) Normalized Delay Contours

Nominal Cu case 22nm node L = 256μm Fanout = 1

Look at changing the interconnect stack and wire properties to improve

• performance (delay, a function of both R and C)

Lower Capacitance Lower Resistance

Re-Engineering the Wires

0.5 1 1.5 2 2.5 0.5 1 1.5 2 RW, normalized to nominal RW(Cu) CW, normalized to nominal CW(Cu) at 22 nm 1 0.8 1.5 2 0.6 0.4

CW/CW(Cu 22nm node) RW/RW(Cu 22nm node) Normalized Delay Contours

Nominal Cu case 22nm node L = 256μm Fanout = 1

Look at changing the interconnect stack and wire properties to improve

• performance (delay, a function of both R and C)
• energy (primarily a function of C)

Decreasing Energy No change in Energy

Re-Engineering the Wires

0.5 1 1.5 2 2.5 0.5 1 1.5 2 RW, normalized to nominal RW(Cu) CW, normalized to nominal CW(Cu) at 22 nm 1 0.8 1.5 2 0.6 0.4

CW/CW(Cu 22nm node) RW/RW(Cu 22nm node) Normalized Delay Contours

Nominal Cu case 22nm node L = 256μm Fanout = 1

Higher resistance can be traded for lower capacitance to achieve lower power with little or no performance cost.

MWCNT Vias

take advantage of the ability to fill vias with arbitrarily high aspect ratios

• to increase interlayer spacing to reduce interlayer coupling

capacitance

• to use ‘reverse scaling’; reduce line thicknesses to reduce

fringing capacitance, without loss of performance

Re-Engineering the Wires

0.5 1 1.5 2 2.5 0.5 1 1.5 2 RW, normalized to nominal RW(Cu) CW, normalized to nominal CW(Cu) at 22 nm 1 0.8 1.5 2 0.6 0.4

CW/CW(Cu 22nm node) RW/RW(Cu 22nm node) Normalized Delay Contours

Nominal Cu case 22nm node L = 256μm Fanout = 1

Higher resistance can be traded for lower capacitance to achieve lower power with little or no performance cost.

Impact on Performance

• Significant energy savings for small hit in delay
• Metal-CNT contact resistance (0.124 vs. 1.1kΩ) has relatively

minor effect on delay Energy (fJ) Delay (ps) Energy vs. Delay

Cu via, Cu line MWCNT via, Cu line (Rvia = 0.124kΩ) MWCNT via, Cu line (Rvia = 1.1kΩ) 22nm node L = 256μm

Impact on Performance

22nm node L = 256μm

greater improvement for higher aspect ratio vias but with diminishing returns Energy (fJ) Delay (ps) Energy vs. Delay

Cu via, Cu line 2X MWCNT via, Cu line 4X MWCNT via, Cu line

Rvia = 0.124kΩ Rvia = 1.1kΩ

Impact on Performance

Advantage diminishes for shorter lines.

22nm node L = 25.6μm Rvia = 0.124kΩ Rvia = 1.1kΩ

Low-Hanging Fruit for CNT Interconnects?

MWCNT vias for semi-global and global wiring

• Lower power or higher performance for semi-global and

global interconnect.

• Relatively low sensitivity to resistance and resistance

variations.

• High reliability.
• No liner required.

Processes already exist that can meet the requirements of this application (low T, one MWCNT per via, ro = rvia) ...... except for high yield.

Our Program

• Develop ordered porous alumina as scaffolds for CNT growth and

characterization

• Develop CNT grow-in-place processes that meet IC implementation

requirements

Templated anodization for independently controlled pore spacing and diameter Ni/Ti, Ni/Pd, Co/Pd, Fe/Pd, Ni/W, and others Catalyst deposition, tube growth, and tube trimming with ion milling 1 MWCNT per pore

+

V I V I

Alumina pore structure after anodizaton Aluminum layer with a modulated topography on Si substrate

Templated Self-Assembly of Porous Alumina

Al SiO2 Si

Initiation sites for pore formation

200nm 200nm

Pore spacing = 180nm Pore diameter =80nm 86V 5% H3PO4 Pore spacing = 200nm Pore diameter =80nm 82V 5% H3PO4 Pore spacing = 200nm Pore diameter =30nm 89V 0.1M H2C2O4

Ordered Porous Alumina with Independently Controlled Diameter and Spacing

single anodization with template single anodization without template

Pre-pattern Symmetry - Hexagonal Pre-pattern Symmetry - Square

86V 5% H3PO4

500nm 500nm

82V 5% H3PO4

Independent Diameter Control

89V 0.1M H2C2O4

500nm

• R. Krishnan and C.V. Thompson, Adv. Mat. 19, 988 (2007)

gas evolution causes delamination

Pore Opening (Barrier Perforation)

‘Conventional’ techniques: New technique:

e.g. W

• J. Oh and C.V. Thompson, Advanced Materials, in press

Vertically Aligned CNT Carpet ½ micron tall growth at 475°C CNT density ~ 2 x 1010 /cm2 Catalyst/underlayer: Fe2nm/Ta30nm/Cu

1 , 3 n m

Low- T CNT Growth on Conductive Substrates

(collaboration with Kevin O’Brien of Intel)

CNT Growth in AAO Scaffold Contact to Conductive Underlayer

BEFORE ION MILLING AFTER ION MILLING

V I V I

5kΩ

AFM Conductivity Measurement

• Ni catalyst electroplated on W underlayer

(below AAO template)

• CNT growth at 490ºC
• All pores filled (with large distribution of

CNT heights)

• Ion milling for uniform CNT height
• Electrical resistance of one pore ~ 5kΩ

CNTs have potential advantages for improved performance or reduced power, as well as high reliability and high chemical stability (no diffusion). Process improvements that are needed for low resistance CNTs

• increased metallic fraction (fmet)
• increased mean free path (λ)
• reduced contact resistance (RC)
• SWCNT or inner MWCNT shell radius (ri)
• highly dense bundles for SWCNTs (ρ)

Longer CNT lines have greater potential resistance advantage over Cu. MWCNT-filled high-aspect-ratio vias offer potential power or performance advantages, even with high resistances.

Summary