Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical - - PowerPoint PPT Presentation

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Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical - - PowerPoint PPT Presentation

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Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 11: February 04, 2020 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 11 Introduction to the Comparators References

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Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 11: February 04, 2020

Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in

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IIT-Bombay Lecture 11 M. Shojaei Baghini

Module 11 Introduction to the Comparators

References

  • Prof. Boris Murmann’s slides from “VLSI Data Conversion Circuits”,

Stanford University, 2013.

  • Section “Latched Comparators” onwards from chapter “Comparators”,

Analog Integrated Circuit Design by T. C. Carusone, D. A. Johns and K. Martin,

  • J. Wiley & Sons, 2012.
  • “Clocked Comparator” from chapter “Submicron CMOS Circuit Design”,

CMOS Mixed-signal Circuit Design by R. Jacob Baker, Wiley India, IEEE press, reprint 2009.

  • “Comparator” from chapter “Nonlinear Analog Circuits”, CMOS Circuit

Design, Layout and Simulation by R. Jacob Baker, Wiley India, IEEE press, 2008.

  • “The StrongArm Latch”, B. Razavi, IEEE Solid-State Circuits Magazine,

Spring 2015.

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IIT-Bombay Lecture 11 M. Shojaei Baghini

Ideal Voltage Comparator

Infinite gain!

  • High gain but not necessarily linear amplification
  • Amplification can happen in discrete time.
  • Clocked versus un-clocked comparator
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IIT-Bombay Lecture 11 M. Shojaei Baghini

Realization of High Gain Operation

  • Common Technique for Amplifiers: Cascade of

Stages

  • Amplification can happen in the form of a regenerative

process due to positive feedback

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IIT-Bombay Lecture 11 M. Shojaei Baghini

Cascade of Gain Stages

R R gm N: Optimal number of stages Av0 = -gm × R , Av= (Av0)N, BW0 = !

"# = ! $ = !

Av0$% where &' = #

()

and C is the equivalent C observed at the output of each stage.

Vout(s) = Vin(s)Av(s) =

∆+,-. /

×

12 !312

4 5 $%/ 5

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IIT-Bombay Lecture 11 M. Shojaei Baghini

Step Response of the Multi-stage Amplifier with Av=10

Optimal number: N=3

  • B. Murmann’s course, Stanford univ., 2013
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IIT-Bombay Lecture 11 M. Shojaei Baghini

How does minimum delay change with increasing Av?

  • B. Murmann’s course, Stanford Univ., 2013
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IIT-Bombay Lecture 11 M. Shojaei Baghini

Analytical Derivation of the Optimum N Av = (Av0)N , td ≈ N × "u × Av0 = N × "u × #$

%/'

dtd/dN = 0 ⇒ #$

%/'- % ') *+(#$) . #$ %/'= 0 ⇒

Nopt ≈ *+(#$) , Av0 = e , td,min ≈ *+(#$) × "u × e e ≈ 2.7 Similar to logic effort-based buffer design!

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IIT-Bombay Lecture 11 M. Shojaei Baghini

Improving the Performance of Each Stage Removing resistors helps to feed the entire current to the capacitors (i.e. only capacitive load as opposed to RC load).

  • B. Murmann’s course, Stanford Univ., 2013
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IIT-Bombay Lecture 11 M. Shojaei Baghini

Performance Improvement using Integrator

  • B. Murmann’s course, Stanford Univ., 2013

There is no limit for the final output but practically supply voltages will limit it.

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IIT-Bombay Lecture 11 M. Shojaei Baghini

Module 12 Latch as a Comparator

References

  • Prof. Boris Murmann’s slides from “VLSI Data Conversion Circuits”,

Stanford University, 2013.

  • Section “Latched Comparators” onwards from chapter “Comparators”,

Analog Integrated Circuit Design by T. C. Carusone, D. A. Johns and K. Martin,

  • J. Wiley & Sons, 2012.
  • “Clocked Comparator” from chapter “Submicron CMOS Circuit Design”,

CMOS Mixed-signal Circuit Design by R. Jacob Baker, Wiley India, IEEE press, reprint 2009.

  • “Comparator” from chapter “Nonlinear Analog Circuits”, CMOS Circuit Design,

Layout and Simulation by R. Jacob Baker, Wiley India, IEEE press, 2008.

  • “The StrongArm Latch”, B. Razavi, IEEE Solid-State Circuits Magazine,

Spring 2015.

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IIT-Bombay Lecture 11 M. Shojaei Baghini

Replacing Cascade of N Integrators with a Closed Loop of Integrators

  • Each inverter is a Gm module driving a capacitive load

and hence behaves as an integrator.

  • A closed loop of two inverters is mimicking cascade of

infinite number of integrators.

VDD VSS VIP VIN !1 !1 !2 !2

CL CL

Latch (regenerative sense amplifier)

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IIT-Bombay Lecture 11 M. Shojaei Baghini

Latch as a Comparator

  • B. Murmann’s course, Stanford Univ., 2013

Latch gain

!! !=

"# $%

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IIT-Bombay Lecture 11 M. Shojaei Baghini

Latch as a Comparator - Example

  • B. Murmann’s course, Stanford Univ., 2013
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IIT-Bombay Lecture 11 M. Shojaei Baghini

Linear Behavior of log(Vdiff(t)) versus t and Initial Condition

  • B. Murmann’s course, Stanford Univ., 2013
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IIT-Bombay Lecture 11 M. Shojaei Baghini

Analysis of Latch Delay

  • K. Martin’s book, 2012
  • B. Murmann’s course, Stanford

Univ., 2013

Td,latch = !latchln

"#$,&#'() "#$,*

C ≈ a × WLCox , 1<a<2 gm ≈ b × +Cox W/L × VGST, 0.5<b<1 (either NMOS or PMOS transistor) ⇒ !latch ≈ d × L2/(+n × VGST) where 1<d<4 Velocity saturation: !latch ≈ a × L/vsat

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IIT-Bombay Lecture 11 M. Shojaei Baghini

End of Lecture 11