Standard Cell Layout Regularity and Pin Access Optimization - - PowerPoint PPT Presentation

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Standard Cell Layout Regularity and Pin Access Optimization - - PowerPoint PPT Presentation

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Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line Wei Ye 1 Bei Yu 1 Yong-Chan Ban 2 Lars Liebmann 3 David Z. Pan 1 1 ECE Department, University of Texas at Austin, Austin, TX, USA 2 System IC R&D Lab, LG

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Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line

Wei Ye1 Bei Yu1 Yong-Chan Ban2 Lars Liebmann3 David Z. Pan1

1ECE Department, University of Texas at Austin, Austin, TX, USA 2System IC R&D Lab, LG Electronics, Seoul, South Korea 3IBM Corporation, Hopewell Junction, NY, USA

May 19, 2015

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Outline

Introduction and Problem Formulation Algorithms Experimental Results Conclusion and Future Work

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Moore’s Law to Extreme Scaling

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Lithography Status & Challenges

Dispearance

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Lithography Status & Challenges

Dispearance

1980 1990 2000 2010 2020 10 1 0.1 um

[Courtesy Intel]

X

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SLIDE 6

AI / Cu / W wires Planar CMOS LE Patterning Transistors

Complexity

Interconnect

2005 2010 2015 2020 2025 [Courtesy ARM]

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SLIDE 7

AI / Cu / W wires Planar CMOS LE FinFET LELE W LI Patterning Transistors

Complexity

Interconnect

2005 2010 2015 2020 2025 [Courtesy ARM]

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SLIDE 8

AI / Cu / W wires Planar CMOS LE FinFET LELE W LI

V0 V0 CB CA TS RSD Poly active M1

gate oxide

Patterning Transistors

Complexity

Interconnect

2005 2010 2015 2020 2025 [Courtesy ARM]

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SLIDE 9

AI / Cu / W wires Planar CMOS LE FinFET LELE W LI 10 nm 7 nm 5 nm 3 nm Patterning Transistors

Complexity

Interconnect

2005 2010 2015 2020 2025 [Courtesy ARM]

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SLIDE 10

AI / Cu / W wires Planar CMOS LE FinFET LELE W LI 10 nm 7 nm 5 nm 3 nm HNW VNW eNVM Cu Doping 3D IC

Opto Connect Graphene CNT

LELELE SADP SAQP EUV LELE EUV EUV EBL EUV DSA Patterning Transistors

Complexity

Interconnect

2005 2010 2015 2020 2025 [Courtesy ARM]

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SLIDE 11

AI / Cu / W wires Planar CMOS LE FinFET LELE W LI 10 nm 7 nm 5 nm 3 nm HNW VNW eNVM Cu Doping 3D IC

Opto Connect Graphene CNT

LELELE SADP SAQP EUV LELE EUV EUV EBL EUV DSA Patterning Transistors

Complexity

Interconnect

2005 2010 2015 2020 2025 [Courtesy ARM]

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SLIDE 12

Solution: Layout Regularity

◮ Extreme lithography friendly ◮ Example: NAND cell [Liebmann et al. SPIE’13] ◮ How about the coming 10nm or even 7nm ?

(a) 90nm (b) 22nm

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More about Middle-Of-Line (MOL)

◮ Local Interconnect (LI) or Intermediate Metallization (IM) ◮ 2 layers: CA (drain ↔ source), CB (via0 ↔ polys) ◮ Improve intra-cell routability ◮ Regular; SADP friendly [Luk-Pat et al, SPIE’13]

V0 V0 CB CA TS RSD Poly active M1

gate oxide

New standard cell structure is required

Metal-1 Poly Metal-2 CA CB

P tracks N tracks M tracks

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Pin Access Challenge

◮ Challenge in advanced tech nodes [Taghavi et al. ICCAD’10] ◮ Local detailed routing congestion ◮ Involve in standard cell design [Xu et al. ISPD’14] ◮ Both length & alignment of pins impact!

Cell C1 Cell C2

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Pin Access Challenge

◮ Challenge in advanced tech nodes [Taghavi et al. ICCAD’10] ◮ Local detailed routing congestion ◮ Involve in standard cell design [Xu et al. ISPD’14] ◮ Both length & alignment of pins impact!

Cell C1 Cell C2 M2 Access Direction

◮ e.g.: C2 has better Pin Accessibility than C1

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Pin Access Value

p(i, j) = hi + hj − α · o(i, j)

◮ hi: track# of pin i ◮ o(i, j): overlapping track# between pins i and j

b a d c Metal-1 pin

Routing track

Metal-2 wire e

If α = 0.6, then:

◮ p(a, c) = 3.8 ◮ p(a, d) = 5 ◮ p(c, d) = 4 ◮ p(a, b) = 5.8 ◮ p(b, d) = 6

Total pin access value for whole standard cell: PA =

m

  • i=1

m

  • j>i

p(i, j)

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How Accurate of Pin Access Value ?

◮ Pin access combination#: through expensive branch-and-bound search ◮ Pin access value: our simple model ◮ Good fidelity !

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URPAO Problem

◮ Unidirectional Routing with Pin Access Optimization (URPAO)

Metal-1 Poly Metal-2 CA CB

P tracks N tracks M tracks

Problem Formulation Input:

  • riginal standard cell; design related parameters

Output: unidirectional (regular) cell layout w. MOL and SADP friendly Objective: minimize the cell wirelength, and maximize the pin access value

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More than Layout Migration

◮ ILP based [Fang et al. ASPDAC’04] ◮ LP based [Heng et al. ISPD’97][Salodkar et al. DAC’13] ◮ Longest-Path based [Tang et al. ICCAD’05]

(a) (b)

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More than Layout Migration

◮ ILP based [Fang et al. ASPDAC’04] ◮ LP based [Heng et al. ISPD’97][Salodkar et al. DAC’13] ◮ Longest-Path based [Tang et al. ICCAD’05]

(a) (b)

Our work is FIRST cell synthesis for

◮ MOL, Regularity, Pin Access, SADP.

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Overall Flow

Dummy Column Insertion Grid Graph Construction Cell Routing Fast Cell Routing ILP Based Cell Routing Design Rules Output 1D Cell Layout Input 2D Cell Layout

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Dummy Column Insertion

◮ Some cross-couple gate connection structures ◮ Insert a dummy poly column to avoid illegal structure

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Grid Graph Construction

◮ 3 routing areas: P tracks, M tracks, N tracks. ◮ 3 terminal types: P-terminals, M-terminals, N-terminals

P tracks M tracks N tracks

Poly column Grid center Intra-cell net Power/Ground net I/O pin net

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Net Topo Enumeration

Example

◮ A net with 2 P-terminals and 1 N terminal ◮ Three possible routes for the net (assuming only one P

, N, M track)

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Overall Flow – ILP Based Cell Routing

Dummy Column Insertion Grid Graph Construction Cell Routing Fast Cell Routing ILP Based Cell Routing Design Rules Output 1D Cell Layout Input 2D Cell Layout

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ILP Based Cell Routing

◮ Binary xp

i = 1 ↔ net i selects route topology rp i

◮ Metric 1: Pin Access PA =

pi,pj∈N

  • rp

i ∈Ri

  • rq

j ∈Rj pp,q

i,j · xp i · xq j

◮ Metric 2: Wire-Length WL =

ni∈N

  • rp

i ∈Ri wp

i · xp i 18 / 35

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ILP Based Cell Routing

◮ Binary xp

i = 1 ↔ net i selects route topology rp i

◮ Metric 1: Pin Access PA =

pi,pj∈N

  • rp

i ∈Ri

  • rq

j ∈Rj pp,q

i,j · xp i · xq j

◮ Metric 2: Wire-Length WL =

ni∈N

  • rp

i ∈Ri wp

i · xp i

Mathematical Formulation

max β · PA − WL s.t.

  • rp

i ∈Ri

xp

i = 1

∀ni ∈ N xp

i ∈ {0, 1}

∀rp

i ∈ Ri , ∀ni ∈ N

xp

i + xq j ≤ 1,

if rp

i , rq j conflict 18 / 35

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ILP Based Cell Routing (cont.)

◮ PA is NOT linear expression due to xp

i · xq j

◮ new variable xp,q

i,j to replace xp i · xq j

◮ additional constraints:

   xp,q

i,j ≥ xp i + xq j − 1

xp,q

i,j ≤ xp i , xp,q i,j ≤ xq j

xp,q

i,j ∈ {0, 1} 19 / 35

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ILP Based Cell Routing (cont.)

◮ PA is NOT linear expression due to xp

i · xq j

◮ new variable xp,q

i,j to replace xp i · xq j

◮ additional constraints:

   xp,q

i,j ≥ xp i + xq j − 1

xp,q

i,j ≤ xp i , xp,q i,j ≤ xq j

xp,q

i,j ∈ {0, 1}

◮ Transform to 0-1 ILP Formulation ◮ Optimal but suffers from runtime overhead

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Overall Flow – Fast Cell Routing

Dummy Column Insertion Grid Graph Construction Cell Routing Fast Cell Routing ILP Based Cell Routing Design Rules Output 1D Cell Layout Input 2D Cell Layout

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Step 1: M Track Assignment

◮ Limited M-track resouce ◮ Block points: poly grids blocked due to connection of Metal-2 wires ◮ net i ∈ BLK(j), if will add block on column j ◮ otherwise, i ∈ NET(j)

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Step 1: M Track Assignment (cont.)

LP Formulation

max

  • i

bi · xi s.t.

  • i∈NET(j)

xi ≤ Tm − |BLK(j)| ∀column j

◮ bi: benefit to assign net i into M-track

Routing track I/O Pins

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Step 2: P/N Track Assignment

2-SAT Formulation

FALSE = ¬xi · xj ⇐ ⇒ TRUE = xi + ¬xj

◮ Optimally solved through strongly connected component ◮ Linear runtime

I/O Pins

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Step 3: I/O Pin Extension

max

m

  • i=1

(l0

i − li) + (ri − r0 i )

s.t. cL ≤ li ≤ l0

i

∀wi ∈ PW r0

i ≤ ri ≤ cR

∀wi ∈ PW ri − li ≥ l0 ∀wi ∈ PW lj − ri ≥ l1 ∀wi, wj ∈ same track

◮ LP formulation, Unimodular ◮ Dual to Min-Cost Flow

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Step 4: Finish All Connections

◮ Vertical connections through CA ◮ Insert poly

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Experimental Setup

Parameters

p(i, j) = hi + hj − α · o(i, j) ⇒ α = 0.6 max β · PA − WL ⇒ β = 0.02

◮ C++; Linux machine with 3.3GHz CPU ◮ Input: Nangate 45nm standard cell library ◮ Target at 10nm technology node with SADP process. ◮ ILP/LP Solver: GUROBI

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Results – Case 1

◮ Input CLKGATE X1

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Results – Case 1

◮ Input CLKGATE X1 ◮ Output [Fast Routing]

(a) 9-track (b) 10-track

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Results – Case 2

◮ Input SDFFRS

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Results – Case 2

◮ Input SDFFRS ◮ Output [Fast Routing]

(a) 9-track (b) 10-track

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Results – 9 V.S. 10 Tracks

On Wire-Length (WL) [ILP Routing]

(a) Total WL (b) M-2 WL

◮ Similar total WL ◮ Different on M-2 WL → impact routing resource

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Results – 9 V.S. 10 Tracks (cont.)

On Pin Access Value (PA) [ILP Routing]

◮ 10-track introduces 8% pin-access value against 9-track ◮ Trade-off: cell height v.s. pin accessibility

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Results – ILP V.S. Fast Cell Routing

Comparison on Wire-Length (WL)

(a) 9-Track (b) 10-Track

◮ Fast cell routing: 0.7% Better total WL

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Results – ILP V.S. Fast Cell Routing (cont.)

Comparison on Pin-Access Value (PA)

(a) 9-Track (b) 10-Track

◮ Fast cell routing: 2% Worse PA

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Results – ILP V.S. Fast Cell Routing (cont.)

Comparison on CPU Runtime

(a) 9-Track (b) 10-Track

◮ Fast cell routing: 10,000× speed-up

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Conclusion and Future Work

◮ First cell synthesis toward better:

◮ MOL structure ◮ Regularity ◮ Pin access ◮ SADP friendly

◮ ILP cell routing: optimal ◮ Fast cell routing: trade-off

Future Work

◮ Flexibility to other lithography techniques ◮ Transistor placement ◮ Standard Cell Characterization

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Thank You !

wye@cerc.utexas.edu bei@cerc.utexas.edu yc.ban@lge.com lliebman@us.ibm.com dpan@cerc.utexas.edu

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