Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line Wei Ye 1 Bei Yu 1 Yong-Chan Ban 2 Lars Liebmann 3 David Z. Pan 1 1 ECE Department, University of Texas at Austin, Austin, TX, USA 2 System IC R&D Lab, LG Electronics, Seoul, South Korea 3 IBM Corporation, Hopewell Junction, NY, USA May 19, 2015 1 / 35
Outline Introduction and Problem Formulation Algorithms Experimental Results Conclusion and Future Work 2 / 35
Moore’s Law to Extreme Scaling 3 / 35
Lithography Status & Challenges Dispearance 4 / 35
Lithography Status & Challenges 10 [Courtesy Intel] Dispearance 1 um 0.1 X 1980 1990 2000 2010 2020 4 / 35
Transistors Patterning Interconnect Complexity [Courtesy ARM] Planar CMOS LE AI / Cu / W wires 2005 2010 2015 2020 2025 5 / 35
Transistors Patterning Interconnect Complexity [Courtesy ARM] LELE FinFET W LI Planar CMOS LE AI / Cu / W wires 2005 2010 2015 2020 2025 5 / 35
M1 V0 V0 Transistors CA Patterning CB Interconnect TS Complexity [Courtesy ARM] Poly LELE RSD gate oxide FinFET active W LI Planar CMOS LE AI / Cu / W wires 2005 2010 2015 2020 2025 5 / 35
Transistors Patterning Interconnect Complexity [Courtesy ARM] LELE FinFET W LI Planar CMOS LE 10 nm 7 nm 5 nm 3 nm AI / Cu / W wires 2005 2010 2015 2020 2025 5 / 35
Opto Connect eNVM EUV DSA Transistors EUV LELE CNT 3D IC VNW Graphene Patterning SAQP EUV EBL Interconnect SADP HNW Complexity [Courtesy ARM] LELELE LELE EUV FinFET W LI Cu Doping Planar CMOS LE 10 nm 7 nm 5 nm 3 nm AI / Cu / W wires 2005 2010 2015 2020 2025 5 / 35
Opto Connect eNVM EUV DSA Transistors EUV LELE CNT 3D IC VNW Graphene Patterning SAQP EUV EBL Interconnect SADP HNW Complexity [Courtesy ARM] LELELE LELE EUV FinFET W LI Cu Doping Planar CMOS LE 10 nm 7 nm 5 nm 3 nm AI / Cu / W wires 2005 2010 2015 2020 2025 5 / 35
Solution: Layout Regularity ◮ Extreme lithography friendly ◮ Example: NAND cell [Liebmann et al. SPIE’13] ◮ How about the coming 10nm or even 7nm ? (a) 90nm (b) 22nm 6 / 35
More about Middle-Of-Line (MOL) M1 ◮ Local Interconnect (LI) or Intermediate Metallization (IM) V0 V0 ◮ 2 layers: CA (drain ↔ source), CB (via0 ↔ polys) CA CB ◮ Improve intra-cell routability ◮ Regular; SADP friendly [Luk-Pat et al, SPIE’13] TS Poly RSD gate oxide active New standard cell structure is required P tracks Poly M tracks Metal-1 Metal-2 N tracks CA CB 7 / 35
Pin Access Challenge ◮ Challenge in advanced tech nodes [Taghavi et al. ICCAD’10] ◮ Local detailed routing congestion ◮ Involve in standard cell design [Xu et al. ISPD’14] ◮ Both length & alignment of pins impact! Cell C1 Cell C2 8 / 35
Pin Access Challenge ◮ Challenge in advanced tech nodes [Taghavi et al. ICCAD’10] ◮ Local detailed routing congestion ◮ Involve in standard cell design [Xu et al. ISPD’14] ◮ Both length & alignment of pins impact! Cell C1 Cell C2 M2 Access Direction ◮ e.g.: C2 has better Pin Accessibility than C1 8 / 35
Pin Access Value p ( i , j ) = h i + h j − α · o ( i , j ) ◮ h i : track# of pin i ◮ o ( i , j ) : overlapping track# between pins i and j If α = 0 . 6 , then: Metal-2 wire ◮ p ( a , c ) = 3 . 8 a Metal-1 pin ◮ p ( a , d ) = 5 Routing track ◮ p ( c , d ) = 4 b e ◮ p ( a , b ) = 5 . 8 c d ◮ p ( b , d ) = 6 Total pin access value for whole standard cell: m m � � PA = p ( i , j ) i = 1 j > i 9 / 35
How Accurate of Pin Access Value ? ◮ Pin access combination#: through expensive branch-and-bound search ◮ Pin access value: our simple model ◮ Good fidelity ! 10 / 35
URPAO Problem ◮ Unidirectional Routing with Pin Access Optimization (URPAO) P tracks M tracks Poly Metal-1 Metal-2 N tracks CA CB Problem Formulation Input: original standard cell; design related parameters Output: unidirectional (regular) cell layout w. MOL and SADP friendly Objective: minimize the cell wirelength, and maximize the pin access value 11 / 35
More than Layout Migration ◮ ILP based [Fang et al. ASPDAC’04] ◮ LP based [Heng et al. ISPD’97][Salodkar et al. DAC’13] ◮ Longest-Path based [Tang et al. ICCAD’05] (a) (b) 12 / 35
More than Layout Migration ◮ ILP based [Fang et al. ASPDAC’04] ◮ LP based [Heng et al. ISPD’97][Salodkar et al. DAC’13] ◮ Longest-Path based [Tang et al. ICCAD’05] (a) (b) Our work is FIRST cell synthesis for ◮ MOL, Regularity, Pin Access, SADP. 12 / 35
Overall Flow Input 2D Cell Layout Design Rules Dummy Column Insertion Grid Graph Construction ILP Based Cell Routing Cell Routing Fast Cell Routing Output 1D Cell Layout 13 / 35
Dummy Column Insertion ◮ Some cross-couple gate connection structures ◮ Insert a dummy poly column to avoid illegal structure 14 / 35
Grid Graph Construction ◮ 3 routing areas: P tracks, M tracks, N tracks. ◮ 3 terminal types: P-terminals, M-terminals, N-terminals P tracks M tracks N tracks I/O pin net Power/Ground net Intra-cell net Poly column Grid center 15 / 35
Net Topo Enumeration Example ◮ A net with 2 P-terminals and 1 N terminal ◮ Three possible routes for the net (assuming only one P , N, M track) 16 / 35
Overall Flow – ILP Based Cell Routing Input 2D Cell Layout Design Rules Dummy Column Insertion Grid Graph Construction ILP Based Cell Routing Cell Routing Fast Cell Routing Output 1D Cell Layout 17 / 35
ILP Based Cell Routing ◮ Binary x p i = 1 ↔ net i selects route topology r p i j ∈ R j p p , q i , j · x p i · x q ◮ Metric 1: Pin Access PA = � � � r p r q p i , p j ∈ N i ∈ R i j i ∈ R i w p i · x p ◮ Metric 2: Wire-Length WL = � � r p n i ∈ N i 18 / 35
ILP Based Cell Routing ◮ Binary x p i = 1 ↔ net i selects route topology r p i j ∈ R j p p , q i , j · x p i · x q ◮ Metric 1: Pin Access PA = � � � r p r q p i , p j ∈ N i ∈ R i j i ∈ R i w p i · x p ◮ Metric 2: Wire-Length WL = � � r p n i ∈ N i Mathematical Formulation β · PA − WL max � x p s.t. i = 1 ∀ n i ∈ N r p i ∈ R i x p ∀ r p i ∈ { 0 , 1 } i ∈ R i , ∀ n i ∈ N x p i + x q if r p i , r q j ≤ 1 , j conflict 18 / 35
ILP Based Cell Routing (cont.) ◮ PA is NOT linear expression due to x p i · x q j ◮ new variable x p , q i , j to replace x p i · x q j ◮ additional constraints: x p , q i , j ≥ x p i + x q j − 1 x p , q i , j ≤ x p i , x p , q i , j ≤ x q j x p , q i , j ∈ { 0 , 1 } 19 / 35
ILP Based Cell Routing (cont.) ◮ PA is NOT linear expression due to x p i · x q j ◮ new variable x p , q i , j to replace x p i · x q j ◮ additional constraints: x p , q i , j ≥ x p i + x q j − 1 x p , q i , j ≤ x p i , x p , q i , j ≤ x q j x p , q i , j ∈ { 0 , 1 } ◮ Transform to 0-1 ILP Formulation ◮ Optimal but suffers from runtime overhead 19 / 35
Overall Flow – Fast Cell Routing Input 2D Cell Layout Design Rules Dummy Column Insertion Grid Graph Construction ILP Based Cell Routing Cell Routing Fast Cell Routing Output 1D Cell Layout 20 / 35
Step 1: M Track Assignment ◮ Limited M-track resouce ◮ Block points: poly grids blocked due to connection of Metal-2 wires ◮ net i ∈ BLK ( j ) , if will add block on column j ◮ otherwise, i ∈ NET ( j ) 21 / 35
Step 1: M Track Assignment (cont.) LP Formulation � b i · x i max i � s.t. x i ≤ T m − | BLK ( j ) | ∀ column j i ∈ NET ( j ) ◮ b i : benefit to assign net i into M-track I/O Pins Routing track 22 / 35
Step 2: P/N Track Assignment 2-SAT Formulation FALSE = ¬ x i · x j ⇐ ⇒ TRUE = x i + ¬ x j ◮ Optimally solved through strongly connected component ◮ Linear runtime I/O Pins 23 / 35
Step 3: I/O Pin Extension m � ( l 0 i − l i ) + ( r i − r 0 i ) max i = 1 s.t. c L ≤ l i ≤ l 0 ∀ w i ∈ PW i r 0 i ≤ r i ≤ c R ∀ w i ∈ PW r i − l i ≥ l 0 ∀ w i ∈ PW l j − r i ≥ l 1 ∀ w i , w j ∈ same track ◮ LP formulation, Unimodular ◮ Dual to Min-Cost Flow 24 / 35
Step 4: Finish All Connections ◮ Vertical connections through CA ◮ Insert poly 25 / 35
Experimental Setup Parameters p ( i , j ) = h i + h j − α · o ( i , j ) α = 0 . 6 ⇒ β = 0 . 02 max β · PA − WL ⇒ ◮ C++; Linux machine with 3.3GHz CPU ◮ Input: Nangate 45nm standard cell library ◮ Target at 10nm technology node with SADP process. ◮ ILP/LP Solver: GUROBI 26 / 35
Results – Case 1 ◮ Input CLKGATE X1 27 / 35
Results – Case 1 ◮ Input CLKGATE X1 ◮ Output [Fast Routing] (a) 9-track (b) 10-track 27 / 35
Results – Case 2 ◮ Input SDFFRS 28 / 35
Results – Case 2 ◮ Input SDFFRS ◮ Output [Fast Routing] (a) 9-track (b) 10-track 28 / 35
Results – 9 V.S. 10 Tracks On Wire-Length (WL) [ILP Routing] (a) Total WL (b) M-2 WL ◮ Similar total WL ◮ Different on M-2 WL → impact routing resource 29 / 35
Results – 9 V.S. 10 Tracks (cont.) On Pin Access Value (PA) [ILP Routing] ◮ 10-track introduces 8% pin-access value against 9-track ◮ Trade-off: cell height v.s. pin accessibility 30 / 35
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