The transistor a switch with no moving parts Gate Source Drain - - PowerPoint PPT Presentation

▶
the transistor a switch with no moving parts
SMART_READER_LITE
LIVE PREVIEW

The transistor a switch with no moving parts Gate Source Drain - - PowerPoint PPT Presentation

Jun 02, 2023 371 likes •936 views

The transistor a switch with no moving parts Gate Source Drain Experimental SiGe transistor (KTH) William Sandqvist william@kth.se Why CMOS? CMOS-Transistors are easy to manifacture CMOS-Transistors are made of ordinary sand

slide-1
SLIDE 1

The transistor – a switch with no moving parts

William Sandqvist william@kth.se

Experimental SiGe transistor (KTH)

Source Drain Gate

slide-2
SLIDE 2

Why CMOS?

William Sandqvist william@kth.se

  • CMOS-Transistors are easy to

manifacture

  • CMOS-Transistors are made of ordinary

sand => cheap raw materials

  • A transistor is easy to get to work as a

switch

slide-3
SLIDE 3

P and N MOS-transistors

William Sandqvist william@kth.se

”Pull Up” ”Pull Down”

1

slide-4
SLIDE 4

The structure of a CMOS-circuit

William Sandqvist william@kth.se

PMOS makes the

  • utput ”1”

NMOS makes the

  • utput ”0”

Two different circuits:

slide-5
SLIDE 5

Inverter

William Sandqvist william@kth.se

(a) Circuit V

f

V

DD

V

x

(b) Truth table and transistor states

  • n
  • ff
  • ff
  • n

1 1 f x T

1

T

2

T

1 T 2

A CMOS-circuit consists of both PMOS and NMOS circuits. The acronym CMOS stands for (Complementary MOS).

Area: Ainverter= 2 Transistors

slide-6
SLIDE 6

CMOS-inverter voltage levels

William Sandqvist william@kth.se

Input voltage Vx Uotput voltage Vf

V

f

V

DD

V

x

T

1

T

2

”0” ”1” ”1” ”0”

slide-7
SLIDE 7

Typical signal-levels for CMOS

William Sandqvist william@kth.se

VLmin VILmax VIHmin VHmax VOHmin VOLmax Margins!

Utput voltages VO and input voltges VI fits together like "hand in a glove", and with a margin to!

slide-8
SLIDE 8

One point is unstable !

William Sandqvist william@kth.se

Vin V

  • ut

Unstable point

VDD VDD

  • CMOS-circuit has a very stable

transfer function

  • At Vin=VDD/2 there is an unstable

unstable point, when both T1 and T2 is conducting.

  • If a circuit temporarily stuck in this

mode, it enters a state called metastability.

  • If this condition lasts for a long time

then the transistors in the circuit can be damaged by the high current.

We will return to metastability ...

slide-9
SLIDE 9

CMOS - Dynamic losses !

William Sandqvist william@kth.se

Classical CMOS has only losses exactly at the vid switching

  • point. The Powerdissipation PF is proportional to the clock-

frequency!

Voltage Supply V ency Clockfrequ f losses Power P V f P

DD C F DD C F 2

⋅ ∝

”1” ”0” ”1”→ ”0” ”1”← ”0”

C C

f f ⋅ 2

slide-10
SLIDE 10

NAND-gate

William Sandqvist william@kth.se

VDD VOH VSS VA VB VA VB VOH VSS(0) VSS(0) VDD(1) VSS(0) VDD(1) VDD(1) VDD(1) VSS(0) VDD(1) VDD(1) VDD(1) VSS(0)

Area: ANAND= 4 Transistors

slide-11
SLIDE 11

NOR-gate

William Sandqvist william@kth.se

VDD VOH VSS VA VB VA VB VOH VSS(0) VSS(0) VDD(1) VSS(0) VDD(1) VSS(0) VDD(1) VSS(0) VSS(0) VDD(1) VDD(1) VSS(0)

Area: ANOR= 4 Transistors

slide-12
SLIDE 12

Negativ logic ?

William Sandqvist william@kth.se

  • We can also turn the concepts and let L (low

voltage) represent a logic 1 and let H (high voltage) represent a logic 0. – This is called negative logic.

  • An AND-function then becomes an OR-function

and vice versa. – Negative logic or positive logic is really unimportant, but traditionally one uses positive logic.

slide-13
SLIDE 13

William Sandqvist william@kth.se

Three-state ?

A CMOS-gate in addition to "1"

  • r "0" is also provided with a

third output state - the three-state ”Z”. ( = unconnected output). If many outputs are connected to the same line ("bus"), you can use one of the out-puts at a time . The other outputs are held in the Three-state condition.

slide-14
SLIDE 14

Three state ’Z’

William Sandqvist william@kth.se

A Y = ' 'Z Y =

slide-15
SLIDE 15

Transmissiongate Pass gate

William Sandqvist william@kth.se

A Q E E

Without going into the circuit details a Pass gate is composed of a PMOS transistor in parallel with an NMOS transistor. The gate is controlled by E (and E'). The pass gate could be compared to "regular" mechanical switch. A signal can go from A to Q, but also backwards from Q to A. Pass gates uses fewer transitors than ordinary gates, but have less drive capability. A Q E Area: A

TG= 2 Transistors

slide-16
SLIDE 16

( Transmission gate pass gate )

A Q E

V

A

VE VOH L L Z L H L H L Z H H H

A Q E E E

William Sandqvist william@kth.se

slide-17
SLIDE 17

What is a multiplexor, MUX?

William Sandqvist william@kth.se

X Y Q S

1 X Y S Q

Q=XS+YS

A multiplexor is a dataselector.

slide-18
SLIDE 18

Simplified drawing

William Sandqvist william@kth.se

X Y Q S X Y Q S

Of the inverter only the ring is left. Wires between the gates are presupposed. Example: MUX

1 X Y S Q

Q=XS+YS

slide-19
SLIDE 19

MUX with pass gates

William Sandqvist william@kth.se

X Y Q Sel Area: Amux= 6 Transistors

2 MOS 2 MOS 2 MOS

slide-20
SLIDE 20

XOR with pass gates

William Sandqvist william@kth.se

A B F = A ⊕ B Area: AXOR= 8 Transistors Hardly

  • bvious?

2 MOS 2 MOS 2 MOS 2 MOS

slide-21
SLIDE 21

( XOR with pass gate )

William Sandqvist william@kth.se

1 1 1 1 1 1 F B A F B = F B =

slide-22
SLIDE 22

William Sandqvist william@kth.se

slide-23
SLIDE 23

Delays in circuits

William Sandqvist william@kth.se

All wires in electronic circuits has capacitance. It takes a while for the voltage to reach the final value. These delays in circuits and between circuits restricts the speed.

slide-24
SLIDE 24

Typical delays

William Sandqvist william@kth.se

NAND, NOR, NOT T NAND = standard T NOT ½ T, 1T (if NAND-gate) NAND-NAND 2T (2 NAND in serial) AND-OR 4T, 3T (NAND-NOT+NOR-NOT) XOR, XNOR, MUX 3…5T XOR, MUX (with TG) 2T

slide-25
SLIDE 25

Optimized structures for MUX

William Sandqvist william@kth.se

Area: AMUX= 2+6+6+6=20 Transistors Delay: TMUX= 5TNAND Area: AMUX=2+4+4 = = 10 Transistors Delay: TMUX= 3TNAND DeMorgan Area: AMUX= 6 Transistors Delay: TMUX= ~2TNAND NAND-NAND AND-OR

Best!

slide-26
SLIDE 26

Optimized structures for XOR

William Sandqvist william@kth.se

Area: AXOR=2+2+6+6+6=22 Transistors Delay: TXOR=5TNAND Area: AXOR=2+2+4+4=12 Transistors Delay: TXOR=3TNAND DeMorgan Area: AXOR=8 Transistorer Delay: TXOR=~2TNAND Area: AXOR=4+4+4+4=16 Transistors Delay: TXOR=3TNAND Nand only

Best!

slide-27
SLIDE 27

Fan-out and Fan-in

William Sandqvist william@kth.se

  • Fan-out - one output drives many inputs. The
  • utput is loaded down by the sum of the inputs

capacitances => delay T is load-dependent.

  • Fan-in - a gate has many inputs. This

means that it has more internal capacitance => the internal delay time Ti (also called the intrinsic delay) becomes larger.

slide-28
SLIDE 28

Gates with multiple inputs

William Sandqvist william@kth.se

VA VB VC VQ

3-input NAND

VDD VSS

A long line of series- connected transistors give slow action! One rarely use gates with more than four inputs. Ti

slide-29
SLIDE 29

High Fan-in is solved with tree structures

William Sandqvist william@kth.se

DeMorgan

For the price of increased gate-depth (delay)

) ( c b a c b a ⋅ ⋅ = ⋅ ⋅ ) ( ) ( d c b a d c b a ⋅ ⋅ ⋅ = ⋅ ⋅ ⋅ d c b a d c b a ⋅ ⋅ ⋅ = ⋅ + ⋅ ) ( ) (

slide-30
SLIDE 30

Moore tree structures

William Sandqvist william@kth.se

) ( ) ( d c b a d c b a + + + = + + + ) ( ) ( d c b a d c b a ⊕ ⊕ ⊕ = ⊕ ⊕ ⊕ ) ( ) ( d c b a d c b a ⊕ ⊕ ⊕ = ⊕ ⊕ ⊕

Can you prove these equivalents? For the price of increased gate- depth (delay), but the effect of internal capacitances had been worse.

slide-31
SLIDE 31

Fan-out

William Sandqvist william@kth.se

(b) Equivalent circuit for timing purposes

x f (a) Inverter that drives n

  • ther inverters

To inputs of n

  • ther inverters

To inputs of n

  • ther inverters

x V

f

N

1

Cn= n⋅C

  • The number of Gate-inputs as a gate drives is

referred to as fan-out

  • All gate inputs that are driven increases the

capacitive load

slide-32
SLIDE 32

Fan-out

William Sandqvist william@kth.se

for n = 1 V

f

for n = 4 V

f

V

DD

Gnd Time

  • Delays from different fan-outs
slide-33
SLIDE 33

Buffer

William Sandqvist william@kth.se

  • A buffer is a circuit that implements

the function f(x) = x ( out = in )

  • The idea of the buffer is to increase

the drive capability of capacitive loads

  • To increase the driving ability one uses larger

transistors

  • Buffers can be sized so that they can drive

larger currents

slide-34
SLIDE 34

High Fan-out – use buffer

William Sandqvist william@kth.se

Non-inverting Buffer Tri-state Buffer High-Fan-Out Buffer

W 3W

En x f f x En x En f Z 1 1 Z 1 1 1

slide-35
SLIDE 35

Critical path

William Sandqvist william@kth.se

f

x0 x1 x2

Which way to the output takes the longest time? x0 x1 x2 ?

2 1 2 2 1

x x x x x x x f + + =

slide-36
SLIDE 36

”Critical path”

William Sandqvist william@kth.se

f

x0 x1 x2

2 1 2 2 1

x x x x x x x f + + =

x0 x1 x2 all pass NOT , AND, and OR, On their way to the output f, but x2 has the load of three inputs, x0 and x1 only two. ”Critical path” becomes x2 !

slide-37
SLIDE 37

William Sandqvist william@kth.se

slide-38
SLIDE 38

Look-up-tables (LUT)

William Sandqvist william@kth.se

0/1 0/1 0/1 0/1

x1 x2 f Two-input LUT

Programmable cells

1 1 1

A LUT with n inputs can realize all combinational functions with n inputs The usual size in an FPGA is n=4

slide-39
SLIDE 39
  • Ex. XOR-function

1 1

x1 x2 f Two-input LUT

Programmed values

1 1 1

Multiplexer

William Sandqvist william@kth.se

1 1 1 1 1 1

2 1

f x x

slide-40
SLIDE 40

William Sandqvist william@kth.se

slide-41
SLIDE 41

7400-series standard chips

William Sandqvist william@kth.se

slide-42
SLIDE 42

Implementing a logic function

William Sandqvist william@kth.se

V

DD x

1

x

2

x

3

f

7404 7408 7432

3 2 2 1

x x x x f + =

slide-43
SLIDE 43

Breadboard simulator

William Sandqvist william@kth.se

3 2 2 1

x x x x f + =

As preparation before the labs you should try to connect the circuits with a breadboard simulator!

slide-44
SLIDE 44

Do you remember? Three-way light control

William Sandqvist william@kth.se

Brown/Vranesic: 2.8.1

Suppose that we need to be able to turn on / off the lamp from three different places. x1 x2 x3 f x1 x2 x3 f

slide-45
SLIDE 45

Three-way light control

William Sandqvist william@kth.se

x1 x2 x3 f

3 2 1 3 2 1 3 2 1 3 2 1

) 7 , 4 , 2 , 1 ( x x x x x x x x x x x x m f + + + = = ∑

slide-46
SLIDE 46

NAND-NAND

William Sandqvist william@kth.se

x1 x2 x3 f 7404 7410 7410 7420 If we change to NAND-NAND all necessary gates are included with the simulator.

slide-47
SLIDE 47

William Sandqvist william@kth.se

#1 #2 #3 #4

1:1

You must enter the pin number in the schematic - otherwise you can get lost!

1:2 2:1

7404 7410 7410 7420

1:3 1:4 2:2 2:13 2:12 1:13 1:12 2:10 2:11 2:9 2:8 3:1 3:13 3:2 3:3 3:4 3:5 3:12 3:6 4:1 4:2 4:4 4:5 4:6

x1 x2 x3

slide-48
SLIDE 48

Simulate!

William Sandqvist william@kth.se

slide-49
SLIDE 49

Prepared simulationfile exists

William Sandqvist william@kth.se

A prepared JBB-simulationfile exists. Put it in the circuit folder. ThreeWaySwitch.cir

slide-50
SLIDE 50

William Sandqvist william@kth.se

slide-51
SLIDE 51

Summary

  • Logic gates can be implemented with the

CMOS technology

  • CMOS-circuits has a delay
  • CMOS circuits has relatively low

powerconsumtion

William Sandqvist william@kth.se

slide-52
SLIDE 52

Facebooks serverhal in Luleå

The operation of the thousands of servers consumes enormous amounts of energy. Fully developed, the plant is requiring 120 MW, more than the SSAB steel mill!

slide-53
SLIDE 53

What would the world be without the CMOS?

slide-54
SLIDE 54

William Sandqvist william@kth.se