MOS Transistor MOS Transistor Professor Chris H. Kim Gate - - PowerPoint PPT Presentation

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MOS Transistor

Professor Chris H. Kim

University of Minnesota

• Dept. of ECE

chriskim@umn.edu www.umn.edu/~chriskim/

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MOS Transistor

Drain Source Gate

Kuroda, IEDM panel

Body

MOS Transistor Current Equation

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Basic Operation (1)

• Device is in cut-off region
• Simply, two back-to-back reverse biased pn diodes.

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Basic Operation (2)

• With a positive gate bias, electrons are pulled toward the

positive gate electrode

• Given a large enough bias, the electrons start to “invert”

the surface (pn type), a conductive channel forms

• Threshold voltage Vt

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Basic Operation (3)

• Current flows from drain to source with a positive drain

voltage

• What is current in terms of Vgs, Vds, Vbs?

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MOS Current

Ids = 0 Vgs< Vt : cut-off Ids = μeCoxW/L ((Vgs-Vt) Vds-0.5Vds2) 0 < Vds < Vgs- Vt : triode (linear) mode Ids = μeCoxW/(2L) (Vgs-Vt)2 0 < Vgs- Vt < Vds : saturation mode

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Channel Length Modulation

ds

• V

L L ζ − =

• Pinch-off depletion layer width increases as the drain

voltage increases

• Extreme case of this is punch-through

) 1 (

ds dsat ds

• dsat

ds

V I V L L I I λ ζ + × = − × =

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Simulation versus Model (NMOS)

• The square-law model doesn’t match well with simulations
• Only fits for low Vgs, low Vds (low E-field) conditions

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Simulation versus Model (PMOS)

• Not as bad as the NMOS device
• Still large discrepancies at high E-field conditions

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Simulation versus Model (Ids vs. Vgs)

• Saturation current does not increase quadratically
• The simulated curves looks like a straight line
• Main reason for discrepancy: velocity saturation

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Velocity Saturation

• E-fields have gone up as dimensions scale
• Unfortunately, carrier velocity in silicon is limited
• Electron velocity saturates at a lower E-field than holes
• Mobility (μe=v/E) degrades at higher E-fields
• Simple piecewise linear model can be used

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Velocity Saturation

c sat c n n c e

E E for v E E for E E E v > = < ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + =

1

1 μ

e sat c

v E μ 2 =

[Toh, Ko, Meyer, JSSC, 8/1988]

• Modeled through a variable mobility
• n=1 for PMOS, n=2 for NMOS
• To get an analytical expression, let’s assume n=1

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Velocity Saturation

• Plug it into the original current equation

L E V V L E V V V V V V V V Wv C V V L E V V V V V L W C I

c t gs c t gs dsat dsat ds dsat t gs sat

• x

dsat ds c ds ds ds t gs

• x

e ds

+ − − = ⎪ ⎪ ⎩ ⎪ ⎪ ⎨ ⎧ > − − < + × ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − − = ∴ ) ( ) ( ) ( ) ( ) ( 1 1 2 ) (

2

μ

Equate the two expressions to get

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Simulation versus Model

• Model incorporating velocity saturation matches fairly

well with simulation

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Unified MOS Model

100 200 300 400 500 600 700 0.2 0.4 0.6 0.8 1 1.2 VDS [V] IDS [V] 0.4V 0.6V 0.8V 1.0V 1.2V

simulation unified model linear saturation

• vel. saturation

Vdsat

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Unified MOS Model Equations

γ - body effect parameter

• Model presented is compact and suitable for hand

analysis.

• Still have to keep in mind the main approximation: that

VDSat is constant.

• But the model still works fairly well.

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Alpha Power Law

α

μ ) ( 2

t gs

• x

e ds

V V C L W I − =

• Simple empirical model for short channel MOS
• Parameter α is between 1 and 2
• α=1-1.2 for short channel

devices

• Parameters α and Vt are fitted

to measured data for minimum square error fitted Vt can be different from physical Vt

[Sakurai and Newton, JSSC 1990]