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Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 1 (December 4, 2000 6:10 pm)

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MOS Transistor Definitions n-type MOS: Majority carriers are electrons. p-type MOS: Majority carriers are holes. Positive/negative voltage applied to the gate (with respect to substrate) enhances the number of electrons/holes in the channel and increases con- ductivity between source and drain. Vt defines the voltage at which a MOS transistor begins to conduct. For volt- ages less than Vt (threshold voltage), the channel is cut off. gate-to-source voltage (Vgs) Drain (Ids) Current Vtn n-channel enhancement MOS

• Vtp

Drain (Ids) Current p-channel enhancement MOS gate-to-source voltage (Vgs) Assume source-to-drain voltage (Vds) is fixed

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 2 (December 4, 2000 6:10 pm)

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MOS Transistor Definitions In normal operation, a positive voltage applied between source and drain (Vds). No current flows between source and drain (Ids = 0) with Vgs = 0 because of back to back pn junctions. For n-MOS, with Vgs > Vtn, electric field attracts electrons creating channel. Channel is p-type silicon which is inverted to n-type by the electrons attracted by the electric field.

Source Drain Gate

Vgs Vds

Gate Oxide n+ n+ p-substrate n-channel GND Drain Source Ids Ids GND

n-MOS transistor

Poly

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 3 (December 4, 2000 6:10 pm)

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n-MOS Enhancement Transistor Physics Three modes based on the magnitude of Vgs: accumulation, depletion and inversion.

Source Drain Gate

Vgs = 0

GND GND

Accumulation Mode

Poly

• +

Vds = 0

• +

n-MOS transistor

+ + + + + + + + + + + + + + + + + + + + + +

• - -
• -

+ + + + + + + + + + + + + + + + + +

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 4 (December 4, 2000 6:10 pm)

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n-MOS Enhancement Transistor Physics

Source Drain Gate

Vgs > 0 and Vgs <= Vt

GND GND

Depletion Mode

Poly

• +

Vds = 0

• +

n-MOS transistor depletion region

+ + + + + + + + + + + + + + + +

• -
• -

+ + + + + + + + + + + + + + + +

Source Drain Gate

Vgs > Vt

GND GND

Inversion Mode

Poly

• +

Vds = 0

• +

n-MOS transistor depletion region inversion region

+ + + + + + + +

• -
• -
• - - - - - - - -
• +

+ + + + + + + + + + + + + + +

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 5 (December 4, 2000 6:10 pm)

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n-MOS Enhancement Transistor With Vds non-zero, the channel becomes smaller closer to the drain. When Vds <= Vgs - Vt (e.g. Vds = 3V, Vgs = 5V and Vt = 1V), the channel reaches the drain (since Vgd > Vt). This is termed linear, resistive or nonsaturated region. Ids is a function of both Vgs and Vds.

Source Drain Gate

Vgs > Vt

GND GND

Inversion Mode

Poly

• +

Vds > 0

• +

n-MOS transistor depletion region inversion region p-substrate

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 6 (December 4, 2000 6:10 pm)

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n-MOS Enhancement Transistor When Vds > Vgs - Vt (e.g. Vds = 5V, Vgs = 5V and Vt = 1V), the channel is pinched off close to the drain (since Vgd < Vt). This is termed saturated region. Ids is a function of Vgs, almost independent

• f Vds.

Source Drain Gate

Vgs > Vt

GND GND

Inversion Mode

Poly

• +

Vds > 0

• +

n-MOS transistor depletion region inversion region p-substrate

• Vgs - Vt

Vds

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 7 (December 4, 2000 6:10 pm)

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MOS Enhancement Transistor MOS transistors can be modeled as a voltage controlled switch. Ids is an important parameter that determines the behavior, e.g., the speed of the switch. What are the parameters that effect the magnitude of Ids? (Assume Vgs and Vds are fixed, e.g. 5V).

• The distance between source and drain (channel length).
• The channel width.
• The threshold voltage.
• The thickness of the gate oxide layer.
• The dielectric constant of the gate insulator.
• The carrier (electron or hole) mobility.

Summary of normal conduction characteristics:

• Cut-off: accumulation, Ids is essentially zero.
• Nonsaturated: weak inversion, Ids dependent on both Vgs and Vds.
• Saturated: strong inversion, Ids is ideally independent of Vds.

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 8 (December 4, 2000 6:10 pm)

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Threshold Voltage Vt is also an important parameter. What effects its value? Most are related to the material properties. In other words, Vt is largely deter- mined at the time of fabrication, rather than by circuit conditions, like Ids. For example, material parameters that effect Vt include: The gate conductor material (poly vs. metal). The gate insulation material (SiO2). The thickness of the gate material. The channel doping concentration. However, Vt is also dependent on Vsb (the voltage between source and substrate), which is normally 0 in dig- ital devices. Temperature: changes by -2mV/degree C for low substrate doping levels.

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 9 (December 4, 2000 6:10 pm)

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Threshold Voltage The expression for threshold voltage is given as: Vt 2φb 2εSiqNA2φb Cox

• V fb

+ + = φb kT q

• NA

Ni

• 

     ln = where Ideal threshold voltage Flat band voltage Bulk potential and NA: Density of the carriers in the doped semiconductor substrate. Ni: The carrier concentration of intrinsic (undoped) silicon. Ni 1.45 10 ×10 cm 3 – at 300 degrees K ( ) = k: Boltzman’s constant. T: temperature. q: electronic charge. kT q

• 25mV (at 300 degrees K)

= εSi: permittivity of silicon εSi 1.06 12 – ×10 Farads/cm = Cox: gate-oxide capacitance. Cox εox tox

• =

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 10 (December 4, 2000 6:10 pm)

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Threshold Voltage Threshold voltage (cont.): Typical values of Vt for n and p-channel transistors are +/- 700mV. Vt 2φb 2εSiqNA2φb Cox

• V fb

+ + = Ideal threshold voltage Flat band voltage and V fb φms Q fc Cox

• –

= where Qfc represents the fixed charge due to imperfections in silicon-oxide interface and doping. and φms is work function difference between gate material and silicon substrate (φgate- φSi). Typical values of Vfb for n/p transistor is -0.9V (with NA = 1016 cm-3) and -0.2V. (See text for examples).

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 11 (December 4, 2000 6:10 pm)

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Threshold Voltage From equations, threshold voltage may be varied by changing: The doping concentration (NA). The oxide capacitance (Cox). Surface state charge (Qfc). As you can see, it is often necessary to adjust Vt. Two methods are common: Change Qfc by introducing a small doped region at the oxide/substrate interface via ion implantation. Change Cox by using a different insulating material for the gate. A layer of Si3N4 (silicon nitride) with a relative permittivity of 7.5 is com- bined with a layer of silicon dioxide (relative permittivity of 3.9). This results in a relative permittivity of about 6. For the same thickness dielectric layer, Cox is larger using the combined material, which lowers Vt.

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 12 (December 4, 2000 6:10 pm)

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Body Effect In digital circuits, the substrate is usually held at zero. The sources of n-channel devices, for example, are also held at zero, except in cases of series connections, e.g., The source-to-substrate (Vsb) may increase at this connections, e.g. VsbN1 = 0 but VsbN2 /= 0. Vsb adds to the channel-substrate potential:

Vdd A B Out P1 P2 N2 N1

Drain of N1 is source of N2 Vt 2φb 2εSiqNA 2φb Vsb + Cox

• V fb

+ + =

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 13 (December 4, 2000 6:10 pm)

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Basic DC Equations Ideal first order equation for cut-off region: Ideal first order equation for linear region: Ideal first order equation for saturation region: with the following definitions: Ids = Vgs Vt ≤ when Ids β Vgs Vt – ( )Vds Vds 2 2

• –

= when 0 V < ds Vgs Vt – < Ids β Vgs Vt – ( )2 2

• =

when V < gs Vt – Vds ≤ β µε tox

• W

L

• 

   = µ = surface mobility of the carriers. ε = permittivity of the gate insulator. tox = thickness of the gate insulator. W and L are the width and length of channel.

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 14 (December 4, 2000 6:10 pm)

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Basic DC Equations Process dependent factors: . Geometry dependent factors: W and L. Voltage-current characteristics of the n- and p-transistors. µCox Cox ε tox

• =

µε tox

• r

where +

• +
• 1->5V

1->5V Vds (V) Ids (mA) VGS = 1V VGS = 2V Vds = Vgs - Vt VGS = 3V VGS = 4V VGS = 5V 1.0 2.0 3.0 4.0 5.0 1 2

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 15 (December 4, 2000 6:10 pm)

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Beta calculation Transistor beta calculation example: Typical values for an n-transistor in 1 micron technology: Compute beta: How does this beta compare with p-devices: n-transistor gains are approximately 2.8 times larger than p-transistors. µn 500cm2 V-sec ⁄ = ε 3.9ε0 3.9 8.85 14 – ×10 F/cm (permittivity of silicon dioxide) × = = tox 20nm = βn 500 3.9 8.85 14 – ×10 × × 0.2 5 – ×10

• W

L

• 86.3W

L

• µA V2

⁄ = = βp 180 3.9 8.85 14 – ×10 × × 0.2 5 – ×10

• W

L

• 31.1W

L

• µA V2

⁄ = =

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 16 (December 4, 2000 6:10 pm)

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Inverter voltage transistor characteristics Inverter DC characteristics Vout Vin A Vin Vout 2.5V VDD 2.5V VDD A B C D E A ;n-device is cut off (Idsn=0), p-device in linear. B Vin Vtn ≤ ≤ ;n-device is in sat., p-device in linear. Vtn Vin VDD 2 ⁄ ∆ –

< <

VDD 2 ⁄ ∆ – Vin VDD 2 ⁄ ∆ + ≤ ≤ ;n-device is in sat., p-device in sat. 2.5V 1.6V 3.6V C D VDD 2 ⁄ ∆ Vin VDD Vtp

+

< < + ;n-device is in linear, p-device in sat. VDD Vtp

+

Vin VDD ≤ ≤ E ;n-device is in linear, p-device in cut off (Idsp=0).

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 17 (December 4, 2000 6:10 pm)

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Beta Ratios Region C is the most important region. A small change in the input voltage, Vin, results in a LARGE change in the output voltage, Vout. This behavior describes an amplifier, the input is amplified at the output. The amplification is termed transistor gain, which is given by beta. Both the n and p-channel transistors have a beta. Varying their ratio will change the characteristics of the output curve.

Vout Vin 2.5V VDD

2.5V

VDD

βn βp ⁄ 0.1 = βn βp ⁄ 1.0 = βn βp ⁄ 10 =

Vout Vin

Beta ratio of n and p-channel transistors varied over two orders

• f magnitude.

p n As ratio is decreased, curve shifts to the right, but the output transition remains sharp.

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 18 (December 4, 2000 6:10 pm)

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Beta Ratios Therefore, the does NOT affect switching performance. What factor would argue for a ratio of 1 for ? Load capacitance ! The time required to charge or discharge a capacitive load is equal when . Since beta is dependent W and L, we can adjust the ratio by changing the sizes of the transistor channel widths, by making p-channel transistors wider than n-channel transistors. βn βp

• βn

βp

• βn

βp

• 1

=

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 19 (December 4, 2000 6:10 pm)

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Noise Margins A parameter that determines the maximum noise voltage on the input of a gate that allows the output to remain stable. Two parameters, Low noise margin (NML) and High noise margin (NMH). NML = difference in magnitude between the max LOW output voltage of the driving gate and max LOW input voltage recognized by the driven gate.

VDD GND Logical high

• utput range

Logical low

• utput range

Logical high input range Logical low input range indeterminate region VOHmin VOLmax VILmax VIHmin

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 20 (December 4, 2000 6:10 pm)

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Noise Margins Ideal characteristic: VIH = VIL = (VOH+VOL)/2. This implies that the transfer characteristic should switch abruptly (high gain in the transition region). VIL found by determining unity gain point from VOH.

Vout Vin 2.5V VDD

2.5V

VDD

βn βp ⁄ 1.0

>

Vout Vin

p n Unity gain points VIH = 3.3 VIL = 2.3 Vtn VDD+Vtp VOH = 5V VOL = 0V NML = 2.3V NMH = 1.7V Assume output

• f driving gate

is stable at supply voltage, e.g., Noise margins are often compromised to improve speed.

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 21 (December 4, 2000 6:10 pm)

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Pseudo-nMOS Inverter Therefore, the shape of the transfer characteristic and the VOL of the inverter is affected by the ratio . In general, the low noise margin is considerably worse than the high noise margin for Pseudo-nMOS. Pseudo-nMOS was popular for high-speed circuits, static ROMs and PLAs.

Vout Vin

2.5V VDD 2.5V VDD

Vout Vin

p n p-device pull-up (load) n-device pull-down (driver) When driver is on, steady-state current flows - not a good choice for low-power Wp/Lp = 1/2 Wp/Lp = 2 Wp/Lp = 4 0V circuits.

βn βp

Principles of VLSI Design Details of the MOS Transistor CMSC 491B/711 22 (December 4, 2000 6:10 pm)

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Pseudo-nMOS Example: Calculation of noise margins: The transfer curve for the pseudo-nMOS inverter can be used to calculate the noise margins of identical pseudo-nMOS inverters.

Vout Vin

VDD 0.8V VDD

Vout Vin

p n Pseudo-nMOS inverter 5V 0.26V 2.2V VOH VIH VOL VIL NMH = VOH - VIH = 5V - 2.2V = 2.8V NML = VIL - VOL = 0.8V - 0.26V = 0.54V (This is quite a bit worse than NMH)