[PPT] - The MOS-transistor Especially short channel effects Especially, PowerPoint Presentation

SLIDE 1

1 Advanced Digital IC-Design

The MOS-transistor

This lecture will Refresh the MOS-transistor function and models Especially short channel effects Especially, short channel effects Digital IC-Design

The Diode

The Diode in an IC-device

Diodes appears in all MOS-transistors Diodes appears in all MOS-transistors (the drain & source area) They have parasitics that affects the performance (speed, power) Diodes should always be backward y biased (negative VBS)

SLIDE 2

2 Diode - The Simplest IC-device

Discrete component IC- structure

p- n+ p+ SiO2 Metal Semi- conductor n+ p+

p

pn-junctions

Advanced Digital IC-Design

The MOS Transistor

The MOS-transistor: An Old Invention

In 1925, Julius Edgar Lilienfeld described the first MOSFET structure

U S Patent in 1930

U.S. Patent in 1930

In early thirties, a similar structure was shown by Oskar Heil

British Patent in 1935

None of them built a working component None of them built a working component The first working MOS-transistor was shown in the early sixties

What is a MOS-transistor?

MOS = ”Metal Oxide Semiconductor”

Polysilicon SiO2 Polysilicon Silicon, doped

Oxide Metal

Semiconductor

SLIDE 3

3 The MOS-transistor (or MOSFET)

Most important device in digital design V d i h Very good as a switch Relatively few parasitics Rather low power consumption High integration density Simple manufacturing Economical for large complex circuits

N-MOS Transistor

Drain Source Gate Bulk

Silicon St t

p- p+ n+ n+ p+ Thin Oxide

Structure

Each box in the layout represents a mask or a step in the process

Mask Layout P-MOS Transistor

Drain Source Gate Bulk

Technologies N W ll

p- p+ p+ p+ n+ N-Well n-

N-Well P-Well Twin-Tub The gate length The gate length sets the name of the technology

How does it Work?

Opens a channel VGS must be lager than a threshold VT

VGS

Gate

VDS drives a current ID

T

ID VDS

Gate Source Drain

SLIDE 4

4 What is a MOS Transistor?

A Switch Circuit Symbol

Ron S G D S G D

VGS VGS

eq

Infinite resistance when VGS < VT Req when VGS ≥ VT VT = Threshold voltage

MOS – a Four Terminal Device

Gate voltage controls the current from drain to source Source connected to lower potential for n-channel devices (often to GND)

Gate

( ) Source connected to higher potential for p-channel devices (often to VDD) Bulk keeps the substrate at a stable potential. If not shown – it is assumed to be connected to the supply/ GND.

Gate Drain Source Drain Source Bulk (Body) Drain Source Bulk (Body)

Important Dimensions

Gate Source Drain

Technology development:

tox

L W

Source

1993: 0.6 um 2003: 65 nm 2013: 18 nm?

L

The technology is named after the gate length L “Diode area”

When VGS is slightly increased Negative charges are attracted

How does the Transistor Work?

g g A depletion region is formed

VGS > 0

p- Depletion Region n+ n+

SLIDE 5

5 How does it Work?

When VGS is increased above VT More negative than positive charges are attracted

VGS > VT

close to the gate (turns to n-type material) A channel is formed (Strong inversion)

p- Depletion Region n+ n+ n-channel

Linear Region (Resistive Operation)

VDS is increased slightly Horizontal E-field from drain to source

VGS > VT

ID

VDS<VGS-VT

A current ID is established

p- Depletion Region n+ n+ n-channel

ID

Linear Region (Resistive Operation)

ID is proportional to the vertical E-field

i.e. to the # of charges attracted by the gate voltage VGS

ID is proportional to the horizontal E-field

i.e. to the charge velocity caused by the drain voltage VDS

VGS forms a vertical E-field

I

´ ( ) 2

DS D n GS T DS

V W I k V V V L = − −

p- n+ n+ID VDS establish a horizontal E-field Electron mobility E-field over the c hannel

n D n

I Q W μ ξ μ ξ = = =

Linear Region (Resistive Operation)

# of charges attracted by the gate Less char ges in drain

GS T DS

Q V V Q V − ∼ ∼ region

DS

V L ξ =

´

(

)

2 ( ) '

D n n n

x

DS S T D GS

V V V k C W I k V L μ = =

From charge conc.

From Horizontal E-Field

SLIDE 6

6

VDS = VGS – VT Strong inversion reached precisely (i.e. VGD = VT)

Saturation Region

No channel close to the drain

VGS > VT

ID

VDS=VGS-VT

p- ”VDS /2" n+

D

n+

Insert VDS = VGS - VT in the linear equation

Saturation Region

´ ( ) 2 ´ ( )( )

D n GS T D n GS T DS DS GS T GS T

W I k V V L W I k V V V V V V V V = − − = − − − −

2

( )( ) 2 ´ ( ) 2

D n GS T n D GS T GS T

L k W I V V L = −

Channel Length Modulation

VDS > VGS-VT

⇒

Pinch off The effective channel length is modulated by VDS

ID

VGS>VT VDS>VGS-VT

g y

DS

Electrons are injected through the depletion region

D n+ n+ L L´

Pinch off

Channel Length Modulation Saturation VDS > VGS-VT

2

´ ( ) (1 )

D n GS T DS

W I k V V V L λ = − +

λ = Empirical constant

SLIDE 7

7 The Threshold Voltage VT

The substrate is slightly doped (p- for NMOS) There are always free electrons in the substrate T f h l d t tt t th ti h

VGS > VT

To form a channel, we need to attract these negative charges The threshold is when the number of negative and positive charges are equal The value of VT is thus set by the p-doping concentration

p- Depletion Region n+ n+ n-channel

The Bulk (Body) Potential

The bulk is most often connected to GND (VDD for PMOS) Negative VSB opens the diode; Not Allowed P iti V k it h d t tt t ti h t

VGS VSB

Positive VSB makes it harder to attract negative charges to the channel That is, the threshold voltage will increase p- n+ n+ p+

Strongly p-doped

) 2 2 (

F SB F T T

V V V φ φ γ − − + − + =

The Threshold Voltage VT

φF = Fermi potential γ increases with the acceptor concentration Low threshold ⇒ Low voltage transistors but they are leaky y y Two threshold voltage technologies can be used for low power

MOS Model for Long Channels

Widely used model for manual calculations

Added to avoid discontinuity

´ ) 1 ( ) ( 2 ´ ; ) 1 )( 2 ) (( ´ ;

2 2 DS T GS n D T GS DS DS DS DS T GS n D T GS DS

C k V V V L W k I V V V V V V V V L W k I V V V μ λ λ = + − = − ≥ + − − = − ≤

y

) 2 2 (

F F T T

x

n n

SB

V V V C k φ φ γ μ − − + − + =

SLIDE 8

8 Velocity & Mobility

The electron (hole) velocity is related to the mobility ( )

μ

2 2

m 0.038 = Electron mobility Vs m 0.013 = Hole mobility Vs

n p

μ μ = =

Typical 0.35μm technology

The mobility is dependent on doping concentration … Often determined empirically Note that the electron mobility is about 3 times higher

Velocity & Mobility

The electron (hole) velocity is related to the mobility The velocity is also dependent on the E-field

( ) μ ( ) ξ

The velocity is also dependent on the E-field ( )

ξ

m s m

n n

υ μ ξ = m s

p p

υ μ ξ =

Velocity Saturation

VDS forms a horizontal E-field An increased E-field leads to higher electron velocity However at a critical E field the velocity saturates due

( )

sat

υ

( ) ξ ( ) ξ

However at a critical E-field , the velocity saturates due to collisions with other atoms

5 m

10 for both electrons and holes s

sat

υ ≈

( )

c

ξ

p- n+ n+

Drain VDS establish a horizontal E-field Source

( )

sat

υ

Velocity Saturation

n n DS

E υ μ =

ξ

The mobility is not constant when velocity

Constant Velocity nt Mobility

sat = 105 m/s

ν

n (m/s)

ν

saturation is reached

Esat EDS [V/um]

Constan

ξ

c

ξ

SLIDE 9

9 ID versus VDS Long-channel ID (mA)

0.5

VGS-VT = 2.5 - 0.43 = 2.07 V

Long channel model Short-channel model

0.4 0.3 0.2

VGS = VDD = 2.5 For both

2.5 0.5 2.0 1.5 1.0 0.1

VDS (V)

VDSAT = 0.63 V

ID versus VGS

6x 10

4

2.5x 10

4

1 2 3 4 5

ID (A)

0.5 1 1.5 2

ID (A)

quadratic d ti linear

0.5 1 1.5 2 2.5

V

GS(V)

0.5 1 1.5 2 2.5

V

GS(V)

quadratic Long Channel Short Channel

ID versus VDS

0 25 0 6

VDS = VGS - VT

Quadratic ID(VGS) Linear ID(VGS) 0 05 0.1 0.15 0.2 0.25 0.2 0.3 0.4 0.5 0.6 ID (mA) VGS= 2.5 VGS= 2.0 VGS= 1.5 VGS= 2.5 VGS= 2.0 VGS= 1.5 VGS= 1.0 ID (mA) 0.5 1 1.5 2 2.5 0.05 0.5 1 1.5 2 2.5 0.1 VDS (V) VGS= 1.0 Long Channel Short Channel

GS

VDS (V)

A first order model of the velocity Model for Manual Analysis

for f

n c

υ μ ξ ξ ξ ξ ξ ξ = ≤ ⎧ ⎪ ⎨ ⎪ ≥ ⎩ for

sat n c c

υ υ μ ξ ξ ξ ⎪ = = ≥ ⎩

SLIDE 10

10 A first order model of the velocity

Model for Manual Analysis

y saturated region:

2

(( ) ) 2

DSAT DSAT n

x

GS T DSAT

V W I C V V V L μ = − −

A Unified Model for Manual Analysis

2 ' min min

(( ) )(1 ) 2 min( )

D n GS T DS

W I k V V V L V V V V V V V λ = − − + = −

min

min( , , )

GS T DS DSAT

V V V V V =

A Unified Model for Manual Analysis

2 '

(( ) )(1 ) 2 Resistive

DS D n GS T DS DS

V W I k V V V V L λ = − − +

' 2 2

( ) (1 ) Saturated 2

n D GS T DS

k W I V V V L V W λ = − +

'

Ve (( locity saturated ) )(1 ) 2

DSAT D n GS T DSAT DS

V W I k V V V V L λ = − − +

Three Regions

VDSAT

0 15

2 V V =

0.63 V

Linear Velocity saturated

0.1 0.15

(mA)

D

I 2 V

GS

V = 1.5 V

GS

V = Saturated VGS-VT (V)

DS

V 0.5 1 2 1 V

GS

V =

SLIDE 11

11 The PMOS Transistor

Velocity saturation is less pronounced for PMOS due to lower mobility

0.4
0.2

0 x 10

4

ID (A)

Assume that all variables are negative!

VGS = -1.0V VGS = -1.5V VGS = 2 0V

2.5
2
1.5
1
0.5
1
0.8
0.6

VDS (V) I

are negative!

VGS = -2.0V VGS = -2.5V

Sub-threshold Region

The sub threshold drain current have an exponential relation to the gate voltage (compare to bipolar)

ln(ID)

Super-threshold region (Super-VT)

1 2 3

VGS (V)

VT

Sub-threshold region (Sub-VT)

MOS Dynamic Behavior

Two Types of Capacitance yp p

Junction Capacitance

Diode areas
Divided in two parts - area and side wall

Gate Capacitance

Gate to Bulk
Gate to Source/ Drain

Drain Source Gate

CGD CGS tox

MOS Capacitances

CDB

n+ n+

CG CSB

Channel Cap. Junction Cap.

Xd

p Overlap Cap.

SLIDE 12

12 Junction Capacitance

CDiff = CBot + CSW Drain/ Source Diffusion

Bottom

CDiff CBot CSW

Don’t count the wall towards the channel

T

w

a r d s a n n e l

Bottom

G a t e T C h a n

Side Wall

W Ls

Junction Capacitance CDiff = CBot + CSW CBot = Cj × Area Cj in F/um2 CSW = CjSW × Perimeter CjSW in F/um

Nonlinear: dependent on the diode voltage

Gate Capacitance

Drain Source Gate

Xd CG = Cox × W × Leff CG depends on the region

CGS CGD CGB

Leff

G

p g

COX in F/um2

Cut off Linear

Channel Capacitance

n+ n+ n+ n+

Saturation

n+ n+

SLIDE 13

13

CGD = Cox × W × Xd CGS = Cox × W × Xd

Overlap Capacitance

Drain Source Gate

Xd

Cox in F/um2

Or CGD = Co × W

d

CGS CGD

Leff

CGS = Co × W

Co in F/um

CGB

Conclusions - Static Behavior

2 '

(( ) )(1 ) 2 Resistive

DS D n GS T DS DS

V W I k V V V V L λ = − − +

' 2 2 '

( ) (1 ) Saturated Ve 2 (( locitysaturated ) )(1 )

n D GS T DS DSAT

k W I V V V L V W I k V V V V λ λ = − + = − − +

( 2 2 )

T T F SB F

V V V γ φ φ = + − + − −

Threshold Voltage

Ve (( locity saturated ) )(1 ) 2

D n GS T DSAT DS

I k V V V V L λ = − − +

A Unified Model for Manual Analysis

2 ' min

(( ) )(1 ) W I k V V V V V λ = +

min min

(( ) )(1 ) 2 min( , , )

D n GS T DS GS T DS DSAT

I k V V V L V V V V V V λ = − − + = −

( 2 2 )

T T F SB F