Transistor-Level Gate Modeling for Nano Transistor-Level Gate - - PowerPoint PPT Presentation

Qin Tang Amir Zjajo Michel Berkelaar Nick van der Meijs

Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations

Contact: Q.tang@tudelft.nl

• Sept. 10, PATMOS 2010

Outline

Motivations Statistical Simplified Transistor Model RDE-based statistical simulator Results Conclusion Motivations

1

Cell modeling for circuit verification

Gate-level modeling unique model for timing, noise and power droop analysis

• Current source model
• unified model for timing, noise and power droop

analysis is feasible

STA: Delay / Sout ------ f(Sin, Ceff)

• Nonlinear resistive Load:
• Input signal : slew

a single linear capacitance value

2

Basic current source model

Ccell Ceff Icell Vout

Sin & Ceff based ramp Ceff Single Switching Assumption (fail for multi-input switching MIS) No internal charge effects

3

Optimization of GLM

Delay & Sout ---- f(Vin1,Vin2,…,V

• ut1,V
• ut2…)

method1 for MIS MIS ? Icell, Ccell ---- f( Vin,V

• ut )

4

Optimization2

PI1 PI2 PIN . . . . . . . . . . . . PO1 PO2 PON Internal Port . . .

Trend: complexity ↑↑↑ Root: black-box property of gate-level model

5

Our solution for modeling

Transistor-level Gate Modeling

• independent of input waveform and output load
• able to capture MIS and internal charge effects
• device-level accuracy
• easy to characterize
• has statistical extension for SSTA

6

Outline

Motivations Statistical Simplified transistor model RDE-based statistical simulator Results Conclusion Statistical Simplified Transistor Model

7

SSTM structure

SSTM: statistical simplified transistor model

ξp: process variation

STM: no process variations

8

Nominal I-V model

Drain current BSIM4-based

1 2

(1 ) (1 ) [1 ( )] 2 ( )

dseff dseff d s gst dseff ds dseff b c th th ds s bs s bs

V V W I JV V V V V V L V V V K V K V                        Simplification

• Vth — no consideration for narrow channel effect & linear

dependence of Vth on Vds

• J — mobility degradation
• λ — channel length modulation, drain induced barrier

lowering (DIBL) and substrate induced body effect.

9

Nominal C-V model

Conventional modeling

Our modeling

Accuracy: analytical method Fast computation: single value

/

ij i j

C Q V   

gate channel capacitances (Cgs, Cgd, Cgb): Junction depletion capacitances (Csb, Cdb):

• constant value in cutoff

and saturation regions;

• Linear function in linear

region single value

10

Statistical extension

1

( , ) ( ) ( )

m ds ds k k k

I t I t t   



  



1

( , ) ( ) ( )

m j j k k k

C t C t t   



  



: random parameter vector : parameter variation from the nominal value p0 : nominal value of the jth capacitance : sensitivities to the random parameters p 

j

C ,   p p   

11

Outline

Motivations Statistical Simplified Transistor Model RDE-based statistical simulation Results Conclusion RDE-based statistical simulator

12

Random Modified Nodal Analysis (MNA)

General analysis flow

DC: initial vector Tran.: solution xs

'

( , , , ) ( ) F x x t p x t x  

Numerical integration methods ( e.g. Backward Euler, Trapezoidal ) Newton-Raphson-like method

'

( , , , ) ( )

x

F x x t p x t x    

Random MNA

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Solving random MNA system

Linearization

' ' ' '

( , , , ) ( , , , ) ( ) ( ) ( ) ( )

s s s s

F x x t p F x x t p C x x A t x x B t           

1st-order Taylor expansion at (xs’, xs , p0)

Reorganization

'

( ) ( ) ( ) ( ) ( )

s x

y x x y t E t y t F t y t       

Random Differential Equation (RDE)

Solution (m. s. integral theorem)

( ) ( ) y t t    

'

( ) ( ) ( ) ( ) ( ) t E t t F t t       

ODE

( ) ( ) ( )

s

x t y t x t  

Assume the initial condition is deterministic

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Statistical output

 

( ) ( )

s

E x t x t 

Analysis output is time-index voltage array for STA, and time-index mean, variance and covariance array for SSTA Only need to simulate once, no need to sample random parameters and then simulate thousands of times. No assumption for the distribution of random process variables

 

 

' 2 1

( ) ( )

m j jk k k

Var x t t Var  



 

     

 

 

1 1 ' 1

( , ) , ,

T i i i m i

Cov x x t diag Var Var t    

 

   

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Probability density function (pdf)

Pr( ) Pr( ( ) ( ) ) Pr( ( ) ) Pr( ( ) ( ) )

r

• t

t V t t V V t V V t t V V t t V V t V

     

              ฀ ฀ ฀

Pr( ) Pr( ( ) ( ) ) Pr( ( ) ) Pr( ( ) ( ) )

f

• t

t V t t V V t V V t V V t t V V t V

     

             ฀ ฀

Vη Vη V (t) V (t-Δt) V (t) V (t-Δt)

rising falling

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Outline

Motivations Statistical Simplified Transistor Model RDE-based statistical simulator Results Conclusion Results

17

STM (nominal SSTM)

Relative error of delay (%) Output slew

5 10 15 20 25 1 2 3 4 5 6 7 8 9

Cload (fF) scaled output rising slew

SSTM results BSIM4 results

5 10 15 20 25 30 0.1 0.2 0.3 0.4 0.5

• 4
• 3
• 2
• 1

1 2

Cload(fF) Slew (ns) Relative Error (%)

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STM for MIS

0.5 1 1.5 2 2.5 3 0.2 0.4 0.6 0.8 1

time (ns) Voltage (V)

2 Vins Vout_ BSIM4 Vout_ STM

Able to capture MIS scenario Results of a NAND2 with simultaneous MIS

19

Power grid analysis

Essential: large current drawn through resistive power supply network Requirement: simulating dynamic current drawn through VDD pins

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

• 3
• 2.5
• 2
• 1.5
• 1
• 0.5

0.5

scaled time s c a le d c u rre n t

SSTM result Spectre result

current drawn by a cell from the power grid

20

Signal integrity verification

0.5 1 1.5 0.2 0.4 0.6 0.8 1

scaled time voltage (V)

noisy input aggressor SSTM output Spectre output

…… .. …… .. Aggressor V_noise V_in driver Active load Cross- cap

21

Statistical evaluation

Standard cells μ (10-9) σ (10-11) CPU time (s) Spectre RDE err(%) Spectre RDE err(%) Spectre RDE INV_X1 0.3777 0.3779 0.00% 3.3407 3.4753 4.03% 91 1.35 INV_X2 0.1986 0.1998 0.60% 1.6113 1.7140 6.37% 91 1.35 INV_X4 0.1148 0.1135 1.10% 0.7103 0.7308 3.96% 91 1.35 BUF_X1 0.3914 0.3915 0.00% 3.7228 3.5644 4.25% 200 5.9 BUF_X2 0.2215 0.2217 0.01% 1.4150 1.5100 7.10% 200 6.0 BUF_X4 0.1554 0.1535 1.20% 0.9995 1.0481 4.80% 200 6.0 NAND_X1 0.3830 0.3842 0.31% 3.4579 3.5618 3.01% 197 6.6 NAND_X2 0.2063 0.2080 0.82% 1.7487 1.7843 2.03% 197 6.6 NOR_X1 0.5040 0.4974 1.31% 4.4148 4.2930 2.70% 198 10 NOR_X2 0.2635 0.2598 1.40% 2.2557 2.1389 5.18% 198 10

Comparison of μ, σ, and CPU time of delay between Spectre and RDE-based method Matlab Vs 1000× MC in Spectre

Average 40× speedup

22

Outline

Motivations Statistical Simplified transistor model RDE-based statistical simulator Results Summary Conclusion

23

Conclusion

Transistor-level gate modeling

• independent of input waveform and output load; able to capture MIS

and internal charge effects; easy to characterize and quite accurate, etc.

• comprehensively handles electrical issues traditionally problematic

for static timing analysis.

Statistical Simplified Transistor Model (SSTM)

• Nominal Ids model: BSIM4-based
• Single value -- Nominal cap model -- analytical model
• Statistical extension: linear Taylor expansion
• Able to handle accuracy limitations of traditional cell models.
• Possible to handle requirements of noise and power analysis
• Compatible with RDE-based simulator for statistical timing

analysis

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