5. Introduction to CMOS Digital Gates Lecture notes: Sec. 4 Sedra - - PowerPoint PPT Presentation

• 5. Introduction to CMOS Digital Gates

Lecture notes: Sec. 4 Sedra & Smith (6th Ed): Sec. 5.1-5.3 Sedra & Smith (5th Ed): Sec. 4.1-4.3

ECE 65, Winter2013, F. Najmabadi

Complementary MOS (CMOS) is based on NMOS/PMOS pairs

• F. Najmabadi, ECE65, Winter 2013, Intro to CMOS (2/11)
• Maximum signal swing: Low State: 0, High State: VDD
• Independent of MOS device parameters!
• Wide noise margin.
• Zero “static” power dissipation (iD = 0 in each state).
• Higher speed compare to a “RTL-type” NMOS inverter

NMOS Inverter

• Replace RD with a PMOS
• “Effective” RD seen by Q1 is

controlled by vi :

• “Infinite” RD when Q1 is ON
• “Very small” RD when Q1 is OFF

CMOS Inverter

Analysis of CMOS Inverter (1)

• F. Najmabadi, ECE65, Winter 2013, Intro to CMOS (3/11)

2 1 2 1 1 2 2 2 1

: KVL 2 & DS1 : KVL GS2 : KVL GS1

SD DD DS

• D

D DS SD DD i DD SG i SG DD i GS

v V v v i i v v V v V v v v V v v − = = = + = − − = → + = − = −

Case 1: vi = 0

ON Q2 OFF Q1

2 1 1

→ > = − = ↓ = → → < = = | |V V v V v i V v v

tp DD i DD SG D tn i GS

ON Q2 OFF Q1

2 2 1 1

= → > = − = ↓ = → → < = =

D tp DD i DD SG D tn i GS

i | |V V v V v i V v v KCL

?

A MOS is ON and iD = 0

• nly if MOS is in triode and vDS = 0
• F. Najmabadi, ECE65, Winter 2013, Intro to CMOS (4/11)

MOS ON: VOV > 0

• MOS in saturation: incorrect!
• MOS in triode:

5 .

2

= → = =

OV OV

• x

n D

V V L W C i µ

[ ]

2 5 .

2

= → = − =

DS DS DS OV

• x

n D

v v v V L W C i µ

When is iD = 0?

• MOS is OFF (VOV < 0)
• No channel is formed, no iD can flow
• MOS is ON (VOV > 0)
• A channel is formed, and iD can flow

but iD = 0 because no voltage is applied to drive iD (vDS = 0) !

& Triode in Q2 ON Q2 | | OFF Q1

2 2 2 1 1 1

= → = → > = − = ↑ ↓ = = → → < = =

SD D tp DD i DD SG DD DS D tn i GS

v i V V v V v V v i V v v

Analysis of CMOS Inverter (2)

• F. Najmabadi, ECE65, Winter 2013, Intro to CMOS (5/11)

Case 1: vi = 0

2 1 2 1 1 2 2 2 1

: KVL 2 & DS1 : KVL GS2 : KVL GS1

SD DD DS

• D

D DS SD DD i DD SG i SG DD i GS

v V v v i i v v V v V v v v V v v − = = = + = − − = → + = − = −

• For vi = VDD, vo = vDS1 = 0 (iD1 = 0, iD2 = 0 )
• Gate remains in this state as long as vi > VDD − |Vtp| (Q2 OFF)

ON Q2 | | OFF Q1

2 2 1 1

= → > = − = ↓ = → → < = =

D tp DD i DD SG D tn i GS

i V V v V v i V v v

Analysis of CMOS Inverter (3)

• F. Najmabadi, ECE65, Winter 2013, Intro to CMOS (6/11)

OFF Q2 | | ON Q1

2 2 1

= → → < = − = ↑ → > = =

D tp i DD SG tn DD i GS

i V v V v V V v v

Case 2: vi = VDD

2 1 2 1 1 2 2 2 1

: KVL 2 & DS1 : KVL GS2 : KVL GS1

SD DD DS

• D

D DS SD DD i DD SG i SG DD i GS

v V v v i i v v V v V v v v V v v − = = = + = − − = → + = − = − OFF Q2 | | & Triode in Q1 ON Q1

2 2 2 1 1 1 DD SD D tp i DD SG DS D tn DD i GS

V v i V v V v v i V V v v = = → → < = − = ↓ ↑ = → = → > = =

• For vi = VDD, vo = vDS1 = 0 (iD1 = 0, iD2 = 0 )
• Gate remains in this state as long as vi > VDD − |Vtp| (Q2 OFF)

OFF Q2 | | ON Q1

2 2 1 1

= → → < = − = ↑ = → > = =

D tp i DD SG D tn DD i GS

i V v V v i V V v v

Transfer function of a CMOS inverter

• F. Najmabadi, ECE65, Winter 2013, Intro to CMOS (7/11)
• Transfer function is “symmetric” for matched transistors:

Vtn=|Vtp| & µn (W/L)n = µp (W/L)p

• During transition from one state to another, iD > 0

CMOS NAND Gate

• F. Najmabadi, ECE65, Winter 2013, Intro to CMOS (8/11)

Truth Table v1 = 0 v2 = 0: vo = VDD v1 = 0 v2 = VDD : vo = VDD v1 = VDD v2 = 0 : vo = VDD v1 = VDD v2 = VDD : vo = 0

Analysis of CMOS NAND Gate (1)

• F. Najmabadi, ECE65, Winter 2013, Intro to CMOS (9/11)

GS2-KVL GS3-KVL GS4-KVL

GS1-KVL:

1 1

v vGS =

GS2-KVL:

1 2 2 1 2 2 DS GS DS GS

v v v v v v − = → + =

GS3-KVL:

1 3 1 3

v V v v v V

DD SG SG DD

− = → + =

GS4-KVL:

2 4 2 4

v V v v v V

DD SG SG DD

− = → + =

KCL:

4 3 2 1 D D D D

i i i i + = =

DS-KVL:

4 3 1 2 4 SD SD DS DS SD DD

v v v v v V = + + =

3 4 2 1 SD DD SD DD

• DS

DS

• v

V v V v v v v − = − = + =

Analysis of CMOS NAND Gate (2)

• F. Najmabadi, ECE65, Winter 2013, Intro to CMOS (10/11)

2 1 3 4 DS DS SD DD SD DD

• v

v v V v V v + = − = − = & Triode in Q4 ON Q4 | | & Triode in Q3 ON Q3 | | ? Q2 OFF Q1

4 4 2 4 3 3 1 3 2 1 1 2 2 1 1 1

= → = → > = − = = → = → > = − = = → − = − = = → → < = =

SD D tp DD DD SG SD D tp DD DD SG D DS DS GS D tn GS

v i V V v V v v i V V v V v i v v v v i V v v ON Q4 | | ON Q3 | | ? Q2 OFF Q1

2 4 1 3 1 1 2 2 1 1 1

→ > = − = → > = − = → − = − = = → → < = =

tp DD DD SG tp DD DD SG DS DS GS D tn GS

V V v V v V V v V v v v v v i V v v ON Q4 | | ON Q3 | | ? Q2 OFF Q1

4 2 4 3 1 3 2 1 1 2 2 1 1 1

= → > = − = = → > = − = = → − = − = = → → < = =

D tp DD DD SG D tp DD DD SG D DS DS GS D tn GS

i V V v V v i V V v V v i v v v v i V v v

• For v1 = 0 & v2 = 0, vo = VDD (iD1 = iD2 = iD3 = iD4 = 0)

Case 1: v1 = 0 & v2 = 0

DD SD DD

• V

v V v = − =

4

Note: Since vDS1 ≥ 0, we can say vGS2 =vDS1 < Vtn and Q2 is OFF!

4 3 2 1 D D D D

i i i i + = =

Analysis of CMOS NAND Gate (3)

• F. Najmabadi, ECE65, Winter 2013, Intro to CMOS (11/11)

2 1 3 4 DS DS SD DD SD DD

• v

v v V v V v + = − = − = & Triode in Q4 ON Q4 | | OFF Q3 | | OFF Q2 & Triode in Q1 ON Q1

4 4 2 4 3 1 3 2 1 1 2 2 1 1 1 1

= → = → > = − = = → → < = − = = → → < − = − = = → = → > = =

SD D tp DD DD SG D tp DD SG D tn DS DS GS DS D tn DD GS

v i V V v V v i V v V v i V v v v v v i V V v v

Case 2: v1 = VDD & v2 = 0

DD SD DD

• V

v V v = − =

4

ON Q4 | | OFF Q3 | | OFF Q2 ON Q1

2 4 3 1 3 2 1 1 2 2 1 1

→ > = − = = → → < = − = = → → < − = − = → > = =

tp DD DD SG D tp DD SG D tn DS DS GS tn DD GS

V V v V v i V v V v i V v v v v V V v v ON Q4 | | OFF Q3 | | OFF Q2 ON Q1

4 2 4 3 1 3 2 1 1 2 2 1 1 1

= → > = − = = → → < = − = = → → < − = − = = → > = =

D tp DD DD SG D tp DD SG D tn DS DS GS D tn DD GS

i V V v V v i V v V v i V v v v v i V V v v

4 3 2 1 D D D D

i i i i + = =

• For v1 = VDD & v2 = 0, vo = VDD (iD1 = iD2 = iD3 = iD4 = 0)

Exercise: Complete the analysis of the truth table of this NAND gate