Working Around the Limits of Working Around the Limits of CMOS - - PowerPoint PPT Presentation

Working Around the Limits of Working Around the Limits of CMOS CMOS CMOS CMOS

Mary Jane Irwin, Penn State Mary Jane Irwin, Penn State

NSF Workshop: Electronic Design Automation – Past, Present, and Future Past, Present, and Future July 8 and 9, 2009

Ab t t Ab t t Abstract Abstract

 

The design constraints of improved performance better energy efficiency increased reliability and



The design constraints of improved performance, better energy efficiency, increased reliability, and constrained design costs challenge EDA researchers as silicon technology continues to scale according to Moore’s Law. However, there are functions that our “standard” silicon technology – CMOS – just doesn’t do well. For functions such as global interconnects, on-chip non-volatile memory, and massive (high bandwidth) input/output, technologies other than CMOS combined with 3D integration holds great

• promise. For example, a network-on-chip in a second layer exploiting optical and/or RF technology can

provide high performance energy efficient and reliable global interconnects SRAM/DRAM memory provide high performance, energy efficient, and reliable global interconnects. SRAM/DRAM memory stacking allows massively parallel memory access helping to mitigate the memory wall and dramatically reducing the large off-chip memory energy consumption. Additionally, stacking emerging non-volatile memory which is immune to radiation-induced soft errors can provide on-chip non-volatile storage while consuming zero standby power. Stacked layers of chemoresistive sensors, mass-sensitive nanoresonators, and biologically-selective FETs fabricated via a directed-assembly approach can provide radically new input/output mechanisms. input/output mechanisms.

 

But to achieve the promise of 3D integration as a way to sustain Moore’s law as well as to enable More- than-Moore requires advances by the EDA community working with the design community, as well as interdisciplinary efforts with chemist, biologists, and material scientists. Fundamental research challenges for the designer include determining a functional partitioning that maximizes the benefits of vertical g g p g connections while achieving optimal performance and energy efficiency, designing the interface circuitry between the CMOS “brains” and the non-CMOS technologies, and ensuring temperature stability across and between layers. T

• meet these challenges, design methodologies and design tools necessary to

implement and simulate/validate 3D architectures which integrate these new technologies and must be developed.

–July 22, 2008 –2

EDA Designer EDA Researcher

–July 22, 2008 –3

Bookkeeping fabric Bookkeeping fabric Bookkeeping fabric Bookkeeping fabric

 No need to be blazingly

fast

 “Old” CMOS suffices

(>250nm)

• Better reliability

L l k

• Less leakage
• No or little process

variation variation

• Existing tools (mostly)

work fine

–July 22, 2008 –4

Adding compute power fabric Adding compute power fabric Adding compute power fabric Adding compute power fabric

 Take advantage of scaling

for compute power (<90nm) No hi hl s sce tible

 Now highly susceptible

to faults, variation, leakage, etc. g

• Must be dynamically

reconfigurable

• Must have to have a way
• Must have to have a way

to monitor the “health” of the compute elements

–July 22, 2008 –5

variability reliability probabilistic behavior

Picture of SET PADOX Structure : Fabrication method for IC-oriented Si single-electron transistors Ono, Y.; Takahashi, Y.; Yamazaki, K.; Nagase, M. Namatsu, H.; Kurihara, K.; Murase, K.

Monitoring the compute fabric Monitoring the compute fabric Monitoring the compute fabric Monitoring the compute fabric

 Performance/power/

p fault “sensors”

• Hardware counters
• Temperature sensors
• …

C t l k b

 Control knobs

• Turn off idle and faulty

cores & links cores & links

• Apply DVFS
• …

–July 22, 2008 –7

NBTI and oxide wearout sensors NBTI and oxide wearout sensors NBTI and oxide wearout sensors NBTI and oxide wearout sensors

LIFO + Control Bits DUT

• L. Co

14.4

20b Register 20b Register 20b Register 20b Counter

Oscillator nverters

21.42 m 40 m 21.42 m

DUT

P1 St d D i Stressed Device P0 T emperature Calibration Device

NAND Oscillator Level Converters

NBTI sensors NBTI sensors NBTI sensors NBTI sensors

164 m 164 m 164 m 164 m 164 m 164 m

10 12

Stress Phase Recovery Phase

 Other kind of

LIFO + Scan Control 1 LIFO + Scan Control LIFO + Scan Control 1 LIFO + Scan Control 1 LIFO + Scan Control LIFO + Scan Control 1 LIFO + Scan Control 1 LIFO + Scan Control LIFO + Scan Control 1

6 8 10

(mV)

sensors

 Number and

16 Oxide Sensors 16 Oxide Sensors 96 m 16 Oxide Sensors 16 Oxide Sensors 16 Oxide Sensors 16 Oxide Sensors 96 m 16 Oxide Sensors 16 Oxide Sensors 96 m 16 Oxide Sensors 16 Oxide Sensors 16 Oxide Sensors 16 Oxide Sensors 96 m 16 Oxide Sensors 16 Oxide Sensors 96 m 16 Oxide Sensors 16 Oxide Sensors 16 Oxide Sensors 16 Oxide Sensors 96 m

2 4 6

Vth (

Vstress = 1.7V Temperature = 130C

location of sensors A ti f

Sensors Sensors Sensors Sensors Sensors Sensors Sensors Sensors Sensors Sensors Sensors Sensors Sensors Sensors Sensors Sensors Sensors Sensors

DISCRETES DISCRETES DISCRETES DISCRETES

2 50 100 150 200

Time (103 s)

Temperature = 130C Sampling Rate = 10s

 Aggregation of

sensor information

196 m 144 Oxide Sensors 96 NBTI Sensors 1 00 196 m 196 m 144 Oxide Sensors 96 NBTI Sensors 1 00 196 m

information

m m m 1500 m m m m m 1500 m m

– David Blaauw, UMich

Adding a communication network Adding a communication network Adding a communication network Adding a communication network

 By moving from 2D to 3D

have many more close neighbors

 Design space exploration  Design space exploration

• Many TSV’s → higher

bandwidth → lower yield

• …

 Other interconnect

technologies like RF and g

• ptical
• Interface circuitry issues
• Thermal issues
• Thermal issues

–July 22, 2008 –10

3D challenges 3D challenges 3D challenges 3D challenges

Architecture/ Design/

Memory-stacked CMP 3D applications Thermal i l ti

Design/ Applications

3D uProc 3D applications

System-level design analysis tools

Cost-driven 3D simulation Physical design Scan

Design automation

Cost-driven 3D EDA tools OpenAccess 3D EDA tools Clocktree T est access Scan design Pre bond

T esting and design-for- testability

synthesis T est scheduling Fault models Pre-bond wafer/die test

testability Process

–11

Nearly Mature Research initiated, Some tools/techniques available No solutions available, research needed

– IBM 11/2002

Adding (nonvolatile) memory Adding (nonvolatile) memory Adding (nonvolatile) memory Adding (nonvolatile) memory

 Use 3D memory stacking

to take advantage of the increased bandwidth and reduced latency

 Will probably require a

redesign of the memory

• rganization/interface
• rganization/interface

 Stacking NVM (MRAM,

PCRAM, …)

• Instant on/off, rad hardened
• Extremely low leakage
• Long write latencies and large
• Long write latencies and large

write energy

–July 22, 2008 –12

MRAM (L2 cache) stacking MRAM (L2 cache) stacking MRAM (L2 cache) stacking MRAM (L2 cache) stacking

2M-SRAM-SNUCA 2M-SRAM-DNUCA 8M Hybrid DNUCA 8M-MRAM-DNUCA 0 8 1 2M SRAM SNUCA 2M SRAM DNUCA 8M Hybrid DNUCA 8M MRAM DNUCA 0.6 0.8 0.2 0.4

galgel apsi equake fma3d swim streamcluster

–13

T

• tal Power Comparison

– Yuan Xie, PSU

Adding I/O Adding I/O Adding I/O Adding I/O

 “Traditional” I/O with

• ptical device stacking

– HP Labs ISCA 08 HP Labs, ISCA 08

 Nontraditional I/O

–July 22, 2008 –14

Nontraditional I/O Nontraditional I/O Nontraditional I/O Nontraditional I/O

 Chemical sensors

Chemical sensors

 Electrofluidic nanowire and

nanobead self assembly

– Tom Mallouk, Chemistry, PSU –Theresa Mayer, EE, PSU y

–15

A A nano nano nose application nose application A A nano nano nose application nose application

 Input – digitized

p g responses from (100x100) gas sensor array

 Memory – threshold

l value storage

 Compute fabric –

neighborhood neighborhood aggregation (e.g., systolic array) systolic array)

–July 22, 2008 –16

More nontraditional I/O More nontraditional I/O More nontraditional I/O More nontraditional I/O

 Biomedical imaging

g g

• Measure tiny magnetic fields

 Use magnetoelectric

g sensors (Magnetic field →

Strain → Electric field) M i i ( i l

• Magnetostriction (materials

that change their shape in response to a magnetic field) p g )

• Piezoelectricity (generate

electric potential in response to applied mechanical stress)

–July 22, 2008 –17

to applied mechanical stress)

Integrated sensor transistor Integrated sensor transistor Integrated sensor transistor Integrated sensor transistor

Fig.4a Integrated sensor systems with associated parastics g g y p Fig.4b Process sequence for the fabrication and direct integration of

• Low parasitics from

elimination of lossy cable

the magnetoelectric cantilever structure. The resonant

• scillation of the

cantilever structure

elimination of lossy cable

• Very low external noise
• Easy batch fabrication for

is capacitively coupled to the floating gate, triggering the transistor drain –18

array demonstration

transistor drain current response.

– Suman Datta, PSU

Adding a power supply Adding a power supply Adding a power supply Adding a power supply

 Energy buffer (battery or

gy ( y capacitor)

• Recharge issues (especially

if the device is implanted)

 Energy scavenging

S RF ib i

• Stray RF sources, vibration,

kinetic energy, thermoelectric generators, g micro wind turbines, etc. (en.wikipedia.org/wiki/Ener gy harvesting ) gy_harvesting )

–July 22, 2008 –19

Material Material Scientists/Engr. Chemists, Physicists Application Designer EDA Researcher pp Domain Experts D i Device Physicists / Fabricators

–July 22, 2008 –20