Lecture 9: Combinational Circuit Design Outline Bubble Pushing - PowerPoint PPT Presentation

Lecture 9: Combinational Circuit Design

Outline � Bubble Pushing � Compound Gates � Logical Effort Example � Input Ordering � Asymmetric Gates � Skewed Gates � Best P/N ratio 10: Combinational Circuits CMOS VLSI Design CMOS VLSI Design 4th Ed. 2

Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. D0 S Y D1 S 10: Combinational Circuits CMOS VLSI Design CMOS VLSI Design 4th Ed. 3

Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. D0 S Y D1 S 10: Combinational Circuits CMOS VLSI Design CMOS VLSI Design 4th Ed. 4

Bubble Pushing � Start with network of AND / OR gates � Convert to NAND / NOR + inverters � Push bubbles around to simplify logic – Remember DeMorgan’s Law Y Y (a) (b) Y Y D (c) (d) 10: Combinational Circuits CMOS VLSI Design CMOS VLSI Design 4th Ed. 5

Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. D0 S Y D1 S 10: Combinational Circuits CMOS VLSI Design CMOS VLSI Design 4th Ed. 6

Compound Gates � Logical Effort of compound gates ( ) = = + = + i i i = + + i i Y A Y A B C Y A B C D Y A B C D E 10: Combinational Circuits CMOS VLSI Design CMOS VLSI Design 4th Ed. 7

Example 4 � The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the two designs. H = 160 / 16 = 10 B = 1 N = 2 D0 D0 S S Y Y D1 D1 S S = + = P 4 1 5 = + = P 2 2 4 = = i = = G (6/3) (1) 2 i G (4 /3) (4/3) 16/9 = = = = F GBH 20 F GBH 160/9 ˆ = = ˆ = = N 4.5 f F N f F 4.2 = + = τ ˆ = ˆ + = τ D Nf P 14 D Nf P 12.4 10: Combinational Circuits CMOS VLSI Design 4th Ed. CMOS VLSI Design 8

Example 5 � Annotate your designs with transistor sizes that achieve this delay. 8 8 8 10 10 8 25 25 10 10 24 Y Y Y Y 25 6 6 12 8 8 25 6 6 8 8 160 * (4/3) / 4.2 = 50 160 * (4/3) / 4.2 = 50 16 160 * 1 / 4.5 = 36 16 16 10: Combinational Circuits CMOS VLSI Design 4th Ed. CMOS VLSI Design 9

Input Order � Our parasitic delay model was too simple – Calculate parasitic delay for Y falling • If A arrives latest? 2 τ • If B arrives latest? 2.33 τ 2 2 Y 6C A 2 x 2C 2 B 10: Combinational Circuits CMOS VLSI Design 4th Ed. CMOS VLSI Design 10

Inner & Outer Inputs � Inner input is closest to output (A) � Outer input is closest to rail (B) � If input arrival time is known – Connect latest input to inner terminal 10: Combinational Circuits CMOS VLSI Design CMOS VLSI Design 4th Ed. 11

Asymmetric Gates � Asymmetric gates favor one input over another � Ex: suppose input A of a NAND gate is most critical – Use smaller transistor on A (less capacitance) – Boost size of noncritical input A Y reset – So total resistance is same � g A = 10/9 2 2 Y � g B = 2 A 4/3 4 � g total = g A + g B = 28/9 reset � Asymmetric gate approaches g = 1 on critical input � But total logical effort goes up 10: Combinational Circuits CMOS VLSI Design 4th Ed. CMOS VLSI Design 12

Symmetric Gates � Inputs can be made perfectly symmetric 2 2 Y A 1 1 B 1 1 10: Combinational Circuits CMOS VLSI Design CMOS VLSI Design 4th Ed. 13

Skew ed Gates � Skewed gates favor one edge over another � Ex: suppose rising output of inverter is most critical – Downsize noncritical nMOS transistor HI-skew unskewed inverter unskewed inverter inverter (equal rise resistance) (equal fall resistance) 2 2 1 A Y A Y A Y 1/2 1 1/2 � Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. – g u = 2.5 / 3 = 5/6 – g d = 2.5 / 1.5 = 5/3 10: Combinational Circuits CMOS VLSI Design 4th Ed. CMOS VLSI Design 14

HI- and LO-Skew � Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. � Skewed gates reduce size of noncritical transistors – HI-skew gates favor rising output (small nMOS) – LO-skew gates favor falling output (small pMOS) � Logical effort is smaller for favored direction � But larger for the other direction 10: Combinational Circuits CMOS VLSI Design CMOS VLSI Design 4th Ed. 15

Catalog of Skew ed Gates Inverter Inverter Inverter NAND2 NAND2 NAND2 NOR2 NOR2 NOR2 4 4 4 2 2 2 2 B 2 2 B B Y Y Y A A 4 4 4 A 2 2 2 A A A 2 2 2 unskewed unskewed unskewed A A A Y Y Y Y Y Y 1 1 1 2 2 2 1 1 1 1 1 1 B B B g u = 1 g u g u = 1 = 1 g u g u g u = 4/3 = 4/3 = 4/3 g u g u = 5/3 g u = 5/3 = 5/3 g d = 1 g d g d = 1 = 1 g d = 4/3 g d g d = 4/3 = 4/3 g d g d g d = 5/3 = 5/3 = 5/3 g avg = 1 g avg = 1 g avg = 4/3 g avg = 4/3 g avg = 5/3 g avg = 5/3 g avg = 1 g avg = 4/3 g avg = 5/3 4 4 2 2 2 2 B B B Y Y Y A A A 4 4 2 2 2 A A A 1 1 HI-skew HI-skew HI-skew A A A Y Y Y Y Y Y 1/2 1/2 1/2 1 1 1/2 1/2 1/2 1/2 B B B g u = 5/6 g u g u = 5/6 = 5/6 g u = 1 g u g u = = g u g u = 3/2 g u = = g d = 5/3 g d g d = 5/3 = 5/3 g d g d = 2 g d = = g d = 3 g d g d = = g avg = 5/4 g avg = 5/4 g avg = 5/4 g avg = g avg = g avg = 3/2 g avg = g avg = 9/4 g avg = 2 2 1 1 1 1 B B B Y Y Y A A A 2 2 1 1 1 A A A 2 2 LO-skew LO-skew LO-skew A A A Y Y Y Y Y Y 1 1 1 2 2 1 1 1 1 B B B g u g u = 4/3 = 4/3 g u g u = = g u g u = = g u = 4/3 g u = 2 g u = 2 g d = 2/3 g d g d = 2/3 = 2/3 g d g d = 1 g d = = g d = 1 g d g d = = g avg = 1 g avg = 1 g avg = 1 g avg = g avg = g avg = 3/2 g avg = g avg = 3/2 g avg = 10: Combinational Circuits CMOS VLSI Design 4th Ed. CMOS VLSI Design 16

Asymmetric Skew � Combine asymmetric and skewed gates – Downsize noncritical transistor on unimportant input – Reduces parasitic delay for critical input A Y reset 2 1 Y A 4/3 4 reset 10: Combinational Circuits CMOS VLSI Design 4th Ed. CMOS VLSI Design 17

Best P/N Ratio � We have selected P/N ratio for unit rise and fall resistance ( μ = 2-3 for an inverter). � Alternative: choose ratio for least average delay � Ex: inverter P – Delay driving identical inverter A – t pdf = (P+1) 1 – t pdr = (P+1)( μ /P) – t pd = (P+1)(1+ μ /P)/2 = (P + 1 + μ + μ /P)/2 – dt pd / dP = (1- μ /P 2 )/2 = 0 – Least delay for P = μ 10: Combinational Circuits CMOS VLSI Design 4th Ed. CMOS VLSI Design 18

P/N Ratios � In general, best P/N ratio is sqrt of equal delay ratio. – Only improves average delay slightly for inverters – But significantly decreases area and power Inverter Inverter NAND2 NAND2 NOR2 NOR2 2 2 2 2 2 2 B B Y Y fastest fastest 2 2 A A 1.414 1.414 A A 2 2 A A Y Y Y Y P/N ratio P/N ratio 1 1 2 2 1 1 1 1 B B g u g u = = 1.15 g u g u = 4/3 = g u g u = 2 = g d g d = 0.81 = g d g d = = 4/3 g d g d = = 1 g avg = g avg = 0.98 g avg = 4/3 g avg = g avg = 3/2 g avg = 10: Combinational Circuits CMOS VLSI Design 4th Ed. CMOS VLSI Design 19

Observations � For speed: – NAND vs. NOR – Many simple stages vs. fewer high fan-in stages – Latest-arriving input � For area and power: – Many simple stages vs. fewer high fan-in stages 10: Combinational Circuits CMOS VLSI Design CMOS VLSI Design 4th Ed. 20