Lecture 9: Combinational Circuit Design Outline Bubble Pushing - - PowerPoint PPT Presentation

Lecture 9:

Combinational Circuit Design

10: Combinational Circuits 2 CMOS VLSI Design CMOS VLSI Design 4th Ed.

Outline

Bubble Pushing Compound Gates Logical Effort Example Input Ordering Asymmetric Gates Skewed Gates Best P/N ratio

10: Combinational Circuits 3 CMOS VLSI Design CMOS VLSI Design 4th Ed.

Example 1

module mux(input s, d0, d1,

• utput y);

assign y = s ? d1 : d0; endmodule

1) Sketch a design using AND, OR, and NOT gates.

D0 S D1 S Y

10: Combinational Circuits 4 CMOS VLSI Design CMOS VLSI Design 4th Ed.

Example 2

2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available.

Y D0 S D1 S

10: Combinational Circuits 5 CMOS VLSI Design CMOS VLSI Design 4th Ed.

Bubble Pushing

Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic – Remember DeMorgan’s Law

Y Y Y D Y (a) (b) (c) (d)

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Example 3

3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available.

Y D0 S D1 S

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Compound Gates

Logical Effort of compound gates

Y A B C = + i Y A B C D = + i i

( )

Y A B C D E = + + i i Y A =

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Example 4

The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160

• units. Estimate the delay of the two designs.

2 2 4 (4 /3) (4/3) 16/9 160/9 ˆ 4.2 ˆ 12.4

N

P G F GBH f F D Nf P τ = + = = = = = = = = + = i

Y D0 S D1 S

Y D0 S D1 S

H = 160 / 16 = 10 B = 1 N = 2

4 1 5 (6/3) (1) 2 20 ˆ 4.5 ˆ 14

N

P G F GBH f F D Nf P τ = + = = = = = = = = + = i

10: Combinational Circuits 9 CMOS VLSI Design CMOS VLSI Design 4th Ed.

6 6 6 6 10 10 Y 24 12 10 10 8 8 8 8 8 8 8 8 25 25 25 25 Y

16 16 160 * (4/3) / 4.2 = 50 160 * 1 / 4.5 = 36

Example 5

Annotate your designs with transistor sizes that achieve this delay.

16 160 * (4/3) / 4.2 = 50

Y Y

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Input Order

Our parasitic delay model was too simple – Calculate parasitic delay for Y falling

• If A arrives latest? 2τ
• If B arrives latest? 2.33τ

6C 2C 2 2 2 2 B A x Y

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Inner & Outer Inputs

Inner input is closest to output (A) Outer input is closest to rail (B) If input arrival time is known – Connect latest input to inner terminal

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Asymmetric Gates

Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical – Use smaller transistor on A (less capacitance) – Boost size of noncritical input – So total resistance is same gA = 10/9 gB = 2 gtotal = gA + gB = 28/9 Asymmetric gate approaches g = 1 on critical input But total logical effort goes up

A reset Y 4 4/3 2 2 reset A Y

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Symmetric Gates

Inputs can be made perfectly symmetric

A B Y 2 1 1 2 1 1

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Skew ed Gates

Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical – Downsize noncritical nMOS transistor Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. – gu = 2.5 / 3 = 5/6 – gd = 2.5 / 1.5 = 5/3

1/2 2 A Y 1 2 A Y 1/2 1 A Y HI-skew inverter unskewed inverter (equal rise resistance) unskewed inverter (equal fall resistance)

10: Combinational Circuits 15 CMOS VLSI Design CMOS VLSI Design 4th Ed.

HI- and LO-Skew

Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. Skewed gates reduce size of noncritical transistors – HI-skew gates favor rising output (small nMOS) – LO-skew gates favor falling output (small pMOS) Logical effort is smaller for favored direction But larger for the other direction

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1/2 2 A Y

Inverter

1 1 2 2 B A Y B A

NAND2 NOR2

1/2 1/2 4 4

HI-skew LO-skew

1 1 A Y 2 2 1 1 B A Y B A 1 1 2 2 gu = 5/6 gd = 5/3 gavg = 5/4 gu = 4/3 gd = 2/3 gavg = 1 gu = 1 gd = 2 gavg = 3/2 gu = 2 gd = 1 gavg = 3/2 gu = 3/2 gd = 3 gavg = 9/4 gu = 2 gd = 1 gavg = 3/2 Y Y 1 2 A Y 2 2 2 2 B A Y B A 1 1 4 4

unskewed

gu = 1 gd = 1 gavg = 1 gu = 4/3 gd = 4/3 gavg = 4/3 gu = 5/3 gd = 5/3 gavg = 5/3 Y 1/2 2 A Y

Inverter

1 1 2 2 B A Y B A

NAND2 NOR2

1/2 1/2 4 4

HI-skew LO-skew

1 1 A Y 2 2 1 1 B A Y B A 1 1 2 2 gu = 5/6 gd = 5/3 gavg = 5/4 gu = 4/3 gd = 2/3 gavg = 1 gu = gd = gavg = gu = gd = gavg = gu = gd = gavg = gu = gd = gavg = Y Y 1 2 A Y 2 2 2 2 B A Y B A 1 1 4 4

unskewed

gu = 1 gd = 1 gavg = 1 gu = 4/3 gd = 4/3 gavg = 4/3 gu = 5/3 gd = 5/3 gavg = 5/3 Y 1/2 2 A Y

Inverter

B A Y B A

NAND2 NOR2 HI-skew LO-skew

1 1 A Y B A Y B A gu = 5/6 gd = 5/3 gavg = 5/4 gu = 4/3 gd = 2/3 gavg = 1 gu = gd = gavg = gu = gd = gavg = gu = gd = gavg = gu = gd = gavg = Y Y 1 2 A Y 2 2 2 2 B A Y B A 1 1 4 4

unskewed

gu = 1 gd = 1 gavg = 1 gu = 4/3 gd = 4/3 gavg = 4/3 gu = 5/3 gd = 5/3 gavg = 5/3 Y

Catalog of Skew ed Gates

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Asymmetric Skew

Combine asymmetric and skewed gates – Downsize noncritical transistor on unimportant input – Reduces parasitic delay for critical input

A reset Y 4 4/3 2 1 reset A Y

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Best P/N Ratio

We have selected P/N ratio for unit rise and fall resistance (μ = 2-3 for an inverter). Alternative: choose ratio for least average delay Ex: inverter – Delay driving identical inverter – tpdf = (P+1) – tpdr = (P+1)(μ/P) – tpd = (P+1)(1+μ/P)/2 = (P + 1 + μ + μ/P)/2 – dtpd / dP = (1- μ/P2)/2 = 0 – Least delay for P = μ

1 P A

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Inverter NAND2 NOR2

1 1.414 A Y 2 2 2 2 B A Y B A 1 1 2 2

fastest P/N ratio

gu = 1.15 gd = 0.81 gavg = 0.98 gu = 4/3 gd = 4/3 gavg = 4/3 gu = 2 gd = 1 gavg = 3/2 Y

Inverter NAND2 NOR2

1 1.414 A Y 2 2 2 2 B A Y B A 1 1 2 2

fastest P/N ratio

gu = gd = gavg = gu = gd = gavg = gu = gd = gavg = Y

P/N Ratios

In general, best P/N ratio is sqrt of equal delay ratio. – Only improves average delay slightly for inverters – But significantly decreases area and power

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Observations

For speed: – NAND vs. NOR – Many simple stages vs. fewer high fan-in stages – Latest-arriving input For area and power: – Many simple stages vs. fewer high fan-in stages