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ENEL 353 F13 Section 02 Slides for Lecture 30 slide 2/21 ENEL 353 F13 Section 02 Slides for Lecture 30 slide 3/21 Previous Lecture Todays Lecture Slides for Lecture 30 ENEL 353: Digital Circuits Fall 2013 Term Completion of an FSM

SLIDE 1

Slides for Lecture 30

ENEL 353: Digital Circuits — Fall 2013 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 20 November, 2013 ENEL 353 F13 Section 02 Slides for Lecture 30 slide 2/21

Previous Lecture

Completion of next-state and output logic design for the Mealy FSM solution to example sequence detection problem. Factoring of FSMs. Reverse-engineering an FSM: Given an FSM circuit, finding a word description of what the FSM does. ENEL 353 F13 Section 02 Slides for Lecture 30 slide 3/21

Today’s Lecture

Completion of an FSM reverse-engineering example. Introduction to timing of sequential logic. Timing parameters for DFFs, and implications of those parameters for timing of synchronous sequential circuits. Related reading in Harris & Harris: Sections 3.4.5–3.4.6, Section 3.5 to the end of 3.5.2. slide 4/21 (This picks up from where the previous lecture ended.) The next three steps are: ◮ Use next-state and output equations to create next-state and output tables. (The next-state table is ready for us on this slide, to save us all some boredom.) ◮ Reduce the next-state table to eliminate unreachable states. ◮ Assign each valid state bit combination a name. Let’s perform the last two of the above steps. S2 S1 S0 A S′ 2 S′ 1 S′ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ENEL 353 F13 Section 02 Slides for Lecture 30 slide 5/21

Completion of the example FSM derivation problem

The final three steps are: ◮ Rewrite next-state and output tables with state names. ◮ Draw state transition diagram. ◮ State in words what the FSM does. Let’s work through these steps. ENEL 353 F13 Section 02 Slides for Lecture 30 slide 6/21

Introduction to timing of sequential logic

For a synchronous sequential circuit design, some of the major timing concerns are . . . ◮ What are sufficient conditions on the D input of a DFF to ensure reliable operations of the DFF? (This is called the “dynamic discipline”.) ◮ Given timing specifications for DFFs and a desired clock period TC, what do those things say about maximum delays in combinational elements in the circuit? ◮ What can go wrong if D inputs of DFFs go 0 → 1 or 1 → 0 at the wrong time? Section 3.5 of Harris & Harris is excellent on these topics. Please read it carefully, more than once! ENEL 353 F13 Section 02 Slides for Lecture 30 slide 7/21

Review: The static discipline

This idea was introduced very early in the course. (See Section 1.6 of Harris and Harris.) The static discipline says that for reliable operation of digital circuit elements, voltages on inputs of circuit elements must not sit in the forbidden zone between VIL and VIH. (Of course, voltages are allowed to pass through the forbidden zone when making low-to-high or high-to-low transitions!) ENEL 353 F13 Section 02 Slides for Lecture 30 slide 8/21

The dynamic discipline

The dynamic discipline has to do with rules about the timing

f transitions on input signals to sequential devices such as

latches and flip-flops. If a sequential circuit design does not comply with the dynamic discipline, the circuit is likely to be unreliable or completely defective. Specifically, for D flip-flops, the dynamic discipline says: The D input to a DFF must not make a 0 → 1

r 1 → 0 transition within an aperture time

surrounding an an active clock edge. The aperture time, as we’ll see, is defined by two DFF timing parameters called the setup time and the hold time. ENEL 353 F13 Section 02 Slides for Lecture 30 slide 9/21

Setup and hold times for DFFs

D Q CLK CLK

tsetup thold

The setup time, tsetup (just ts in some textbooks) is a short time interval before a rising edge on CLK. The hold time, thold (just th in some textbooks) is a short time interval after a rising edge on CLK. Proper DFF behaviour—Q copies D on rising edges of CLK—is guaranteed only if D does not change value within the aperture time defined by the setup and hold times.

SLIDE 2 ENEL 353 F13 Section 02 Slides for Lecture 30 slide 10/21

Setup and hold times—example 1

The gold rectangles mark apertures defined by setup and hold times for a DFF. CLK D Q

t0 t1

Here D is stable through both apertures, so Q reliably takes values of 0 shortly after t0 and 1 shortly after t1. ENEL 353 F13 Section 02 Slides for Lecture 30 slide 11/21

Setup and hold times—example 2

CLK D Q

t0 t1

Here D changes after the aperture around t1 is over, so Q remains 0 for the clock cycle following t1. ENEL 353 F13 Section 02 Slides for Lecture 30 slide 12/21

Setup and hold times—example 3

Here there is a violation of the setup-and-hold-time rules around t1. CLK D Q

t0 t1

? ? ? What happens to Q after t1? There are multiple possibilities, which we’ll get to later. For now, what’s important to know is that circuit behaviour following t1 is unpredictable. ENEL 353 F13 Section 02 Slides for Lecture 30 slide 13/21

D flip-flop clock-to-Q delays: tccq and tpcq

D Q CLK As mentioned as few lectures ago, the Q

utput of a DFF does not change at exactly

the same time as its input CLK signal rises—there is a short delay. tccq is the clock-to-Q contamination delay. It takes at least this much time for a rising edge of CLK to cause a change in Q. tpcq is the clock-to-Q propagation delay. It takes no more than this much time for a rising edge of CLK to cause a change in Q. ENEL 353 F13 Section 02 Slides for Lecture 30 slide 14/21

tsetup, thold, tccq, and tpcq, all on one timing diagram

CLK tccq tpcq t setup

utput(s)

input(s) t hold Let’s write down some notes about how to read this diagram. Image is Figure 3.37 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc. ENEL 353 F13 Section 02 Slides for Lecture 30 slide 15/21

Where do DFF timing parameters come from?

The range of possible clock-to-Q delays from as fast as tccq to as slow as tpcq reflects factors such as ◮ variation in VDD ◮ variation in temperature ◮ minor variations in physical dimensions and chemical composition of transistors ◮ various other physical factors. tsetup and thold are worst-case numbers over all allowable

perating conditions for a circuit.

ENEL 353 F13 Section 02 Slides for Lecture 30 slide 16/21

A generic piece of synchronous sequential logic

Below is a small part of a larger synchronous sequential circuit. Registers R1 and R2 are collections of DFFs that all have the same tsetup, thold, tccq, and tpcq. C L CLK R2 R1 Q1 D1 Q2 D2 The combinational element shown has contamination delay tcd and propagation delay tpd. We’ll assume that signal D1 meets the setup and hold time requirements of R1, and look at whether signal D2 meets the setup and hold time requirements of R2. ENEL 353 F13 Section 02 Slides for Lecture 30 slide 17/21

Setup time constraint

C L CLK R2 R1 Q1 D1 Q2 D2 Recall that TC stands for the clock period. Suppose there is a rising edge of CLK at time t0. What must be true so that there is no setup time violation at R2 at the next rising edge of CLK, at time t0 + TC? Let’s do the simple math, then make some remarks. ENEL 353 F13 Section 02 Slides for Lecture 30 slide 18/21

Hold time constraint

C L CLK R2 R1 Q1 D1 Q2 D2 Suppose there is a rising edge of CLK at time t0. What must be true so that there is no hold time violation at R2 at the same rising edge of CLK, also at time t0? Again, let’s do some simple math, then make some remarks.

SLIDE 3 ENEL 353 F13 Section 02 Slides for Lecture 30 slide 19/21

Hold time constraint: Direct Q-to-D connection

Let’s look at this special case, in which there is no combinational delay between a Q output of a DFF and the D input of another DFF. Q1 D1 CLK FF1 FF2 D2 Q2 Let’s assume that the DFFs are identical, and that setup and hold time conditions are satisfied by the D1 input to FF1. What must be true so that there is no hold time violation at FF2 at the same rising edge of CLK, also at time t0? Let’s do the very simple math, then make some remarks. ENEL 353 F13 Section 02 Slides for Lecture 30 slide 20/21

Remark about resettable, settable, and enabled flip-flops

The textbook doesn’t mention this, but it’s good to know. For DFFs with EN inputs, and/or synchronous reset or set inputs, the EN, reset and set inputs have tsetup and thold parameters that are similar to the tsetup and thold parameters for the D input. For DFFs with asynchronous reset or set inputs, the timing parameters for those inputs are typically a minimum width for a reset or set pulse, along with a minimum gap between when reset or set is turned off and a rising edge of the clock. ENEL 353 F13 Section 02 Slides for Lecture 30 slide 21/21

Upcoming topics

Examples of timing calculations for synchronous sequential logic. Introduction to the concept of clock skew. Introduction to the concept of metastability. Related reading in Harris & Harris: Section 3.5.2–3.5.4.