ENEL 353 F13 Section 02 Slides for Lecture 32 slide 2/19 ENEL 353 F13 Section 02 Slides for Lecture 32 slide 3/19 Previous Lecture Today’s Lecture Slides for Lecture 32 Completion of a timing analysis example. ENEL 353: Digital Circuits — Fall 2013 Term Introduction to clock skew . Adjustment of setup and hold time constraint inequalities Steve Norman, PhD, PEng Implications of DFF timing parameters for timing of to account for clock skew. synchronous sequential circuits. Electrical & Computer Engineering What can happen when setup and hold time constraints are Examples of timing analysis for synchronous sequential logic. Schulich School of Engineering University of Calgary violated? Introduction to metastability . 25 November, 2013 Related reading in Harris & Harris: Sections 3.5.2–3.5.4 slide 4/19 slide 5/19 slide 6/19 ENEL 353 F13 Section 02 Slides for Lecture 32 ENEL 353 F13 Section 02 Slides for Lecture 32 ENEL 353 F13 Section 02 Slides for Lecture 32 Completion of a timing analysis example Solutions for the hold time violation Introduction to clock skew Solution 1: Add delay on Solution 2: Switch the two Available inverters have t cd = 9 ns and t pd = 15 ns. the path from the Foo flip-flops. One inverter This list is review. It’s a list of sufficient conditions for DFF timing parameters, in ns, are given in the table. output to the Bar input. provides enough delay. building a synchronous sequential circuit . . . family CLK CLK CLK 1. Every element in the circuit either is a register or is parameter Foo Bar combinational. Y Y t setup 2 20 Y 2. At least one element is a register. t hold 1 7 FooLogic BarTron BarTron FooLogic 3. All registers receive the same clock signal. t pcq 8 50 FooLogic BarTron t ccq 5 30 4. Every cyclic path in the circuit passes through at least DIY (Do It Yourself): Check that there are no hold-time one register. A student tests the circuit with a 1 MHz CLK input, expecting violations in either of the above circuits. to see a 250 kHz square wave on Y. The circuit doesn’t work Unfortunately, the laws of physics make it very hard to Remark: It is generally a bad idea to combine flip-flops with because of a hold time violation at the BarTron DFF input. perfectly satisfy condition 3 . . . very different timing parameters in a single synchronous What can be done to fix the circuit? design! ENEL 353 F13 Section 02 Slides for Lecture 32 slide 7/19 ENEL 353 F13 Section 02 Slides for Lecture 32 slide 8/19 ENEL 353 F13 Section 02 Slides for Lecture 32 slide 9/19 Introduction to clock skew , continued Minimization of clock skew; definition of t skew Clock skew, setup and hold time constraints It takes time for a voltage change to propagate along a wire. CLK1 and CLK2 come from the same clock source, but due to Clock skew is the name given to the problem having having clock skew, clock edges might not arrive at R1 and R2 at clock different registers get clock edges at slightly different names. exactly the same time. source Delay from the clock source to clock inputs cannot be CLK1 CLK2 avoided. Circuit designers try to minimize clock skew by D1 Q1 D2 Q2 making all the source-to-input delays very close to the C CLK1 CLK2 CLK3 L same . (Because delays can be affected by factors such as R1 R2 D1 Q1 D2 Q2 D3 Q3 electrical noise, clock skew can’t be made zero just by making Review: If it happens that that there is no clock skew, then all clock-source-to-clock-input wires the same length.) we know for safe operation this must be true . . . R1 R2 R3 In a synchronous sequential circuit, t skew is defined as the worst-case difference in times of arrival of an active clock edge t pd for C L ≤ T C − ( t pcq + t setup ) ( t setup constraint) Clock edges received by R1 are early relative to clock edges at any two registers in the circuit. t cd for C L ≥ t hold − t ccq ( t hold constraint) received by R2. Clock edges received by R3 are late relative to clock edges received by R2.
ENEL 353 F13 Section 02 Slides for Lecture 32 slide 12/19 Clock skew and the setup time constraint slide 10/19 Clock skew and the hold time constraint slide 11/19 CLK1 CLK2 CLK1 CLK2 Summary of timing constraints in the presence of D1 Q1 D2 Q2 D1 Q1 D2 Q2 C C clock skew L L R1 R2 R1 R2 Suppose CLK2 is early relative to CLK1. For reliable Now suppose CLK2 is late relative to CLK1. For reliable operation, what must be true about the speed of the operation, what must be true about the speed of the setup time constraint: t pd ≤ T C − ( t pcq + t setup + t skew ) combinational logic? (The gold rectangle shows the t setup / t hold combinational logic? (Again, the gold rectangle shows the hold time constraint: t cd ≥ t hold + t skew − t ccq aperture for R2.) t setup / t hold aperture for R2.) Things to note: CLK1 CLK1 t pcq t ccq ◮ If we set t skew = 0, we get the same inequalities we Q1 Q1 derived in the previous lecture. t pd t cd ◮ Both inequalities say that as t skew increases, the designer’s D2 D2 job gets more difficult. t pd may need to be reduced on some paths, and t cd may need to be increased on other CLK2 CLK2 paths. t skew t skew slide 13/19 slide 14/19 slide 15/19 ENEL 353 F13 Section 02 Slides for Lecture 32 ENEL 353 F13 Section 02 Slides for Lecture 32 ENEL 353 F13 Section 02 Slides for Lecture 32 Review of a simple timing example An odd-looking example circuit Example responses to a setup time violation Connecting one signal to CLK Here we assume that Q 3:0 = 0000 before the rising edge of Here there is a violation of the setup-and-hold-time rules four register inputs will let D Q 3 CLK. around t 1 . us make a point about the Q 2 variety of possible responses CLK CLK Q 1 to an aperture time Q 0 D violation. D Q 3 The DFFs in the register are very close to identical, but not Q ? ? ? perfectly so, due to minor manufacturing variations. Q 2 t 0 t 1 If the setup and hold time rules are respected, all four Q Q 1 values will copy D on each rising edge of CLK, with a delay in What happens to Q after t 1 ? There are multiple the range from t ccq to t pcq . Q 0 possibilities . What might happen if the setup and hold time rules are Let’s look at these multiple possibilities in more detail. violated? Let’s make some remarks about these responses. ENEL 353 F13 Section 02 Slides for Lecture 32 slide 16/19 ENEL 353 F13 Section 02 Slides for Lecture 32 slide 17/19 ENEL 353 F13 Section 02 Slides for Lecture 32 slide 18/19 Metastability in latches and flip-flops A mechanical analogy for metastability Why is metastability dangerous? There are two stable places for the ball: the bottom of In normal operation the Q and Q signals of a latch or flip-flop valley 0, and the bottom of valley 1. The key problem is this: t res will sometimes be much longer will sit in one or the other of two stable states: than t pcq . Sometimes t res may be as long as one whole clock ( Q , Q ) = (0 , 1) or ( Q , Q ) = (1 , 0). period in a synchronous system. Metastability is the name given to a kind of abnormal hill Of course, the output signal of a flip-flop or latch is typically behaviour in which the voltages of the Q and Q signals both an input signal to one or more other circuit elements. sit approximately halfway between 0 and V DD for some valley 0 valley 1 period of time called t res , the resolution time . A circuit element with a metastable input will probably generate an incorrect output. So metastability in a single DFF Given a gentle nudge, the ball will move a little, but stay in Once the resolution time has passed, the latch or flip-flop goes could cause an entire synchronous circuit to behave valley 0. Given a strong push, the ball will roll over the hill and to (“resolves” to) one or the other of its stable states. settle in valley 1. incorrectly, possibly getting the circuit into a state from which t res is random , differing in length from one instance of it can’t recover. What if the ball is given a push that gives it just enough metastability to the next. energy to get to the top of the hill and stop?
ENEL 353 F13 Section 02 Slides for Lecture 32 slide 19/19 Upcoming topics More about metastability. The problem of asynchronous inputs to synchronous systems. Counters and shift registers. Memory arrays. Related reading in Harris & Harris: Sections 3.5.4–3.5.5, 5.4, 5.5
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