CMOS Inverter: Power Dissipation and Sizing CMOS Inverter Power - - PowerPoint PPT Presentation

SLIDE 1

1

CMOS Inverter: Power Dissipation and Sizing

Professor Chris H. Kim

University of Minnesota

• Dept. of ECE

chriskim@umn.edu

CMOS Inverter Power Dissipation

3

Where Does Power Go in CMOS?

• Switching power

– Charging capacitors

• Leakage power

– Transistors are imperfect switches

• Short-circuit power

– Both pull-up and pull-down on during transition

• Static currents

– Biasing currents, in e.g. memory

4

Dynamic Power Consumption

( ) ( )

∫ ∫ ∫

= = = =

→

DD

V DD L

• ut

L DD T T DD DD DD

V C dv C V dt t i V dt t P E

2 1

( ) ( )

∫ ∫ ∫

= = = =

DD

V DD L

• ut
• ut

L T T L

• ut

C C

V C dv v C dt t i v dt t P E

2

2 1

iL

2 1 DD LV

C E =

→

V

in

V

• ut

CL V

DD

SLIDE 2

2

5

Dynamic Power Consumption

• One half of the energy from the supply is

consumed in the pull-up network and one half is stored on CL

• Energy from CL is dumped during the 1→0

transition

2 1 DD LV

C E =

→ 2

2 1

DD L R

V C E =

iL

V

in

V

• ut

CL V

DD

2

2 1

DD L C

V C E =

6

Circuits with Reduced Swing

C L V dd V dd V dd -V Th

( )

Th DD DD L

V V V C E − =

→1

7

Dynamic Power Consumption

Power = Energy/transition • Transition rate = CLVDD

2 • f0→1

= CLVDD

2 • f • P0→1

= CswitchedVDD

2 • f

• Power dissipation is data dependent –

depends on the switching probability

• Switched capacitance Cswitched = CL • P0→1

8

Transition Activity and Power

• Energy consumed in N cycles, EN:

EN = CL • VDD2 • n0→1 n0→1 – number of 0→1 transitions in N cycles f V C N n f N E P

DD L N N N avg

⋅ ⋅ ⋅ ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ = ⋅ =

→ ∞ → ∞ → 2 1

lim lim f N n

N

⋅ =

→ ∞ → → 1 1

lim α f V C P

DD L avg

⋅ ⋅ ⋅ =

→ 2 1

α

SLIDE 3

3

9

Short Circuit Current

• Short circuit current is usually well controlled

20 −0.5 0.5 1 1.5 2 2.5 40 60 Isc (A) x 10−4 CL = 20 fF CL = 100 fF CL = 500 fF time (s)

Vin Vout CL VDD Isc ∼ 0 Vin Vout CL VDD Isc = IMAX

Large load Small load

10

Transistor Leakage

• Transistors that are supposed to be off - leak

Input at VDD Input at 0

VDD 0V VDD

ILeak

VDD 0V VDD

ILeak

11

N p+ p+

Reverse Leakage Current +

• Vdd

GATE

IDL = JS × A

JS = 10-100 pA/mm2 at 25 deg C for 0.25um CMOS JS doubles for every 9 deg C! Much smaller than transistor leakage in deep submicron

Diode Leakage Sizing of an Inverter Chain

SLIDE 4

4

13

Inverter Chain

If CL is given:

• How many stages are needed to minimize the

delay?

• How to size the inverters?

May need some additional constraints.

In Out CL

14

Inverter Delay

• Minimum length devices, L=0.25um
• Assume that for WP = 2WN =2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
• Analyze as an RC network

W N unit N unit unit P unit P

R R W W R W W R R = = ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ ≈ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ =

− − 1 1

tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL Delay (D): 2W W

unit unit gin

C W W C 3 =

Load for the next stage:

15

Inverter with Load

Load (CL) Delay

Assumptions: no load -> zero delay CL tp = k RWCL RW RW Wunit = 1 k is a constant, equal to 0.69 for step input

16

Inverter with Load

Load Delay

Cint CL Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint) = Delay (Intrinsic) + Delay (Load) CN = Cunit CP = 2Cunit 2W W

SLIDE 5

5

17

Delay Formula

( ) ( ) ( )

γ / 1 / 1 ~

int

f t C C C kR t C C R Delay

p int L W p L int W

+ = + = +

Cint = γCgin with γ ≈ 1 f = CL/Cgin - effective fanout R = Runit/W ; Cint =WCunit tp0 = 0.69RunitCunit

18

Apply to Inverter Chain

CL In Out 1 2 N tp = tp1 + tp2 + …+ tpN

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ +

+ j gin j gin unit unit pj

C C C R t

, 1 ,

1 ~

L N gin N i j gin j gin p N j j p p

C C C C t t t = ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + = =

+ = + =

∑ ∑

1 , 1 , 1 , 1 ,

, 1

1 = γ

19

Optimal Tapering for Given N

Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N Minimize the delay, find N - 1 partial derivatives Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1 Size of each stage is the geometric mean of two neighbors

• each stage has the same effective fanout (Cout/Cin)
• each stage has the same delay

1 , 1 , , + −

=

j gin j gin j gin

C C C

20

Optimum Delay and Number of Stages

1 ,

/

gin L N

C C F f = =

When each stage is sized by f and has same eff. fanout f:

N F

f =

( )

N p p

F Nt t + = 1

Minimum path delay Effective fanout of each stage:

SLIDE 6

6

21

Example

CL= 8 C1 In Out C1 1 f f2

2 8

3

= = f

CL/C1 has to be evenly distributed across N = 3 stages:

22

Optimum Number of Stages

For a given load, CL and given input capacitance Cin Find optimal number of stages, N, and optimal sizing, f

( )

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + = + = f f f F t F Nt t

p N p p

ln ln ln 1 /

/ 1

γ γ γ ln 1 ln ln

2

= − − ⋅ = ∂ ∂ f f f F t f t

p p

γ γ

For γ = 0, f = e, N = lnF f F N C f C F C

in N in L

ln ln with = = ⋅ =

( )

f f γ + = 1 exp

23

Optimum Effective Fanout f

Optimum f for given process defined by γ

( )

f f γ + = 1 exp

fopt = 3.6 for γ=1

0.5 1 1.5 2 2.5 3 2.5 3 3.5 4 4.5 5 γ fopt

24

Impact of Loading on tp

With self-loading γ=1

1 1.5 2 2.5 3 3.5 4 4.5 5 1 2 3 4 5 6 7

f Normalized delay

SLIDE 7

7

25

Normalized Delay Function of F

( )

γ / 1

N p p

F Nt t + =

( )

1 with , 1 = + = γ

N p p

F Nt t

26

Buffer Design

1 1 1 1 8 64 64 64 64 4 2.8 8 16 22.6

N f tp 1 64 65 2 8 18 3 4 15 4 2.8 15.3