CMOS Inverter Two Inverters N Well VDD Share power and ground V - - PowerPoint PPT Presentation

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CMOS Inverter Two Inverters N Well VDD Share power and ground V - - PowerPoint PPT Presentation

Sep 01, 2023 140 likes •241 views

The CMOS Inverter: A First Glance V CMOS Inverter DD V in V out Professor Chris H. Kim C L University of Minnesota Dept. of ECE chriskim@umn.edu www.umn.edu/~chriskim/ 2 CMOS Inverter Two Inverters N Well VDD Share power and ground V

slide-1
SLIDE 1

1

CMOS Inverter

Professor Chris H. Kim

University of Minnesota

  • Dept. of ECE

chriskim@umn.edu www.umn.edu/~chriskim/

2

The CMOS Inverter: A First Glance

Vin Vout C

L

V

DD

3

CMOS Inverter

Polysilicon In Out VDD GND PMOS is wider Metal 1 NMOS

Out In VDD PMOS NMOS

Contacts N Well Length Width 4

Two Inverters

Connect in Metal

Share power and ground Abut cells

VDD

slide-2
SLIDE 2

2

Voltage Transfer Characteristics

6

CMOS Inverter First-Order DC Analysis

VOL = 0 VOH = VDD VM = f(Rn, Rp)

VDD VDD Vin = VDD Vin = 0 Vout Vout Rn Rp

7

CMOS Inverter Load Characteristics

IDn V

  • ut

Vin = 2.5 Vin = 2 V

in = 1.5

Vin = 0 V

in = 0.5

V

in = 1

NMOS V

in = 0

V

in = 0.5

V

in = 1

V

in = 1.5

Vin = 2 V

in = 2.5

Vin = 1 V

in = 1.5

PMOS

8

CMOS Inverter VTC

Vout V

in 0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5 NMOS lin PMOS off NMOS sat PMOS sat NMOS off PMOS lin NMOS sat PMOS lin NMOS lin PMOS sat

slide-3
SLIDE 3

3

9

Simulated Inverter VTC (hspice)

0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5

Vin(V) V out(V)

10

Switching Threshold as a Function of Transistor Ratio

100 101 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 M

V (V) W

p/Wn

11

VTC as a function of VDD

0.05 0.1 0.15 0.2 0.05 0.1 0.15 0.2 V

in(V)

V

  • ut (V)

0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5 V

in(V)

V

  • ut(V)

Gain=-1

12

Impact of Sizing

0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5

Wider PMOS Wider NMOS Symmetrical

Vin(V) V

  • ut(V)
slide-4
SLIDE 4

4

13

Impact of Process Variations

0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5

Vin(V) V

  • ut(V)

Fast PMOS Slow NMOS Fast NMOS Slow PMOS Nominal

14

DC Operation Voltage Transfer Characteristic

V(x) V(y) VOH VOL V

M

VOH VOL f V(y)=V(x) Switching Threshold Nominal Voltage Levels

VOH = f(VOL) VOL = f(VOH) VM = f(VM)

15

Mapping between analog and digital signals

VIL VIH Vin Slope = -1 Slope = -1 V OL V OH Vout

“ 0” VOL VIL VIH VOH Undefined Region “ 1”

16

Definition of Noise Margins

Noise margin high Noise margin low

VIH VIL Undefined Region "1" "0" VOH VOL NMH NML Gate Output Gate Input

slide-5
SLIDE 5

5

17

Example: CMOS Inverter DC Properties

  • VOH = VDD = 2.5V
  • VOL = 0V
  • VIL = 1.05V
  • VIH = 1.45V
  • NMH =1.05V
  • NML = 1.05V
  • VM = 1.2V

18

Regenerative Property

v0 v1 v3 finv(v) f(v) v3

  • ut

v2 in

Regenerative Non-Regenerative

v2 v1 f(v) finv(v) v3

  • ut

v0 in

19

Regenerative Property

A chain of inverters v0 v1 v2 v 3 v 4 v 5 v 6

2 V (Volt) 4 v0 v1 v2 t (nsec) 2 1 1 3 5 6 8 10

Simulated response

Propagation Delay

slide-6
SLIDE 6

6

21

Computing the Capacitances

VDD VDD Vin Vout M1 M2 M3 M4 Cdb2 Cdb1 Cgd12 Cw Cg4 Cg3 Vout2 Fanout Interconnect Vout Vin CL Simplified Model 22

CMOS Inverter: Transient Response

tpHL = f(Ron.CL) = 0.69 RonCL

(a) Low-to-high (b) High-to-low

Vout Vout Rn Rp VDD VDD Vin = VDD Vin = 0 CL CL

23

Delay Definitions

Vout tf tpHL tpLH tr t Vin t 90% 10% 50% 50%

24

CMOS Inverter Propagation Delay

VDD Vout Vin= VDD CL

Iav t pHL= CL Vdd /2 Iav

slide-7
SLIDE 7

7

25

Transient Response

0.5 1 1.5 2 2.5 x 10

  • 10
  • 0.5

0.5 1 1.5 2 2.5 3 t (sec) V

  • ut(V)

tpLH tpHL

tp = 0.69 CL (Reqn+Reqp)/2

26

Design for Performance

  • Keep capacitances small
  • Increase transistor sizes

– watch out for self-loading!

  • Increase VDD

27

Delay as a function of VDD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

Vdd (V) tp(normalized)

28

Device Sizing

(for fixed load) Self-loading effect: Intrinsic capacitances dominate

2 4 6 8 10 12 14 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 x 10

  • 11

Size tp (sec)

slide-8
SLIDE 8

8

29

NMOS/PMOS ratio

tpLH tpHL tp

β = Wp/Wn

1 1.5 2 2.5 3 3.5 4 4.5 5 3 3.5 4 4.5 5x 10

  • 11

β

tp (sec)

30

Impact of Rise Time on Delay

tpHL(nsec) 0.35 0.3 0.25 0.2 0.15 trise (nsec) 1 0.8 0.6 0.4 0.2

tp = tstep(i) + htstep(i-1)

31

Fan-in and Fan-out

N

Fan-out N Fan-in M

M

32

Ring Oscillator

v0 v1 v5 v1 v2 v0 v3 v4 v5

T = 2 × tp × N

slide-9
SLIDE 9

9

33

CMOS Properties

  • Full rail-to-rail swing
  • Symmetrical VTC
  • Propagation delay function of load

capacitance and resistance of transistors

  • No static power dissipation (ignoring

leakage current)

  • Direct path current during switching