Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of - - PowerPoint PPT Presentation

▶
static power sca of sub 100 nm cmos asics and the
SMART_READER_LITE
LIVE PREVIEW

Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of - - PowerPoint PPT Presentation

Sep 26, 2023 170 likes •741 views

RUHR-UNIVERSITT BOCHUM Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments Thorben Moos Ruhr University Bochum, Horst Grtz Institute for IT Security, Germany August 28th, 2019 Section 1

slide-1
SLIDE 1

RUHR-UNIVERSITÄT BOCHUM

Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments

Thorben Moos Ruhr University Bochum, Horst Görtz Institute for IT Security, Germany August 28th, 2019

slide-2
SLIDE 2

Section 1 Introduction

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 1

slide-3
SLIDE 3

RUHR-UNIVERSITÄT BOCHUM

What’s known?

Introduction

  • CMOS logic gates and memory elements have a data dependent static power

consumption

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 2

slide-4
SLIDE 4

RUHR-UNIVERSITÄT BOCHUM

What’s known?

Introduction

  • CMOS logic gates and memory elements have a data dependent static power

consumption

  • Leakage currents increase significantly by down-scaling the physical feature size of

transistors

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 2

slide-5
SLIDE 5

RUHR-UNIVERSITÄT BOCHUM

What’s known?

Introduction

  • CMOS logic gates and memory elements have a data dependent static power

consumption

  • Leakage currents increase significantly by down-scaling the physical feature size of

transistors

  • Attacks on crypto primitives exploiting this data dependency have been

demonstrated in practice for FPGAs [CHES 2014] and ASICs [DATE 2015/2017]

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 2

slide-6
SLIDE 6

RUHR-UNIVERSITÄT BOCHUM

What’s known?

Introduction

  • CMOS logic gates and memory elements have a data dependent static power

consumption

  • Leakage currents increase significantly by down-scaling the physical feature size of

transistors

  • Attacks on crypto primitives exploiting this data dependency have been

demonstrated in practice for FPGAs [CHES 2014] and ASICs [DATE 2015/2017]

  • When clock control is obtained by an adversary, measurements with a very low noise

influence can be recorded

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 2

slide-7
SLIDE 7

RUHR-UNIVERSITÄT BOCHUM

What’s known?

Introduction

  • CMOS logic gates and memory elements have a data dependent static power

consumption

  • Leakage currents increase significantly by down-scaling the physical feature size of

transistors

  • Attacks on crypto primitives exploiting this data dependency have been

demonstrated in practice for FPGAs [CHES 2014] and ASICs [DATE 2015/2017]

  • When clock control is obtained by an adversary, measurements with a very low noise

influence can be recorded

  • Control over the operating conditions significantly enhances the ability to extract

secrets, even though it accelerates device degradation

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 2

slide-8
SLIDE 8

RUHR-UNIVERSITÄT BOCHUM

Setup

Introduction

Temp.: 90 °C Humid.: 10 %

Vdd

+

  • +
  • ASIC

Oscilloscope Low-Pass Filter DC Amplifier Climate Chamber Board + ASIC

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 3

slide-9
SLIDE 9

RUHR-UNIVERSITÄT BOCHUM

Setup

Introduction

Temp.: 90 °C Humid.: 10 %

Vdd

+

  • +
  • ASIC

Oscilloscope Low-Pass Filter DC Amplifier Climate Chamber Board + ASIC

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 3

slide-10
SLIDE 10

RUHR-UNIVERSITÄT BOCHUM

Setup

Introduction

Temp.: 90 °C Humid.: 10 %

Vdd

+

  • +
  • ASIC

Oscilloscope Low-Pass Filter DC Amplifier Climate Chamber Board + ASIC

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 3

slide-11
SLIDE 11

RUHR-UNIVERSITÄT BOCHUM

Setup

Introduction

Temp.: 90 °C Humid.: 10 %

Vdd

+

  • +
  • ASIC

Oscilloscope Low-Pass Filter DC Amplifier Climate Chamber Board + ASIC

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 3

slide-12
SLIDE 12

RUHR-UNIVERSITÄT BOCHUM

Setup

Introduction

Temp.: 90 °C Humid.: 10 %

Vdd

+

  • +
  • ASIC

Oscilloscope Low-Pass Filter DC Amplifier Climate Chamber Board + ASIC

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 3

slide-13
SLIDE 13

RUHR-UNIVERSITÄT BOCHUM

Setup

Introduction

Temp.: 90 °C Humid.: 10 %

Vdd

+

  • +
  • ASIC

Oscilloscope Low-Pass Filter DC Amplifier Climate Chamber Board + ASIC

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 3

slide-14
SLIDE 14

RUHR-UNIVERSITÄT BOCHUM

Setup

Introduction

Temp.: 90 °C Humid.: 10 %

Vdd

+

  • +
  • ASIC

Oscilloscope Low-Pass Filter DC Amplifier Climate Chamber Board + ASIC

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 3

slide-15
SLIDE 15

RUHR-UNIVERSITÄT BOCHUM

ASICs

Introduction (a) 65nm ASIC layout (b) 90nm ASIC layout

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 4

slide-16
SLIDE 16

Section 2 Influence of Operating Conditions

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 5

slide-17
SLIDE 17

RUHR-UNIVERSITÄT BOCHUM

Target

1024-bit HF Register

To evaluate the influence of

  • perating conditions, choose

an instance that leaks a lot:

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 6

slide-18
SLIDE 18

RUHR-UNIVERSITÄT BOCHUM

Target

1024-bit HF Register

To evaluate the influence of

  • perating conditions, choose

an instance that leaks a lot: 1024-bit HF Input Register

  • filled either with 0s or 1s
  • average fanout of 11

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 6

slide-19
SLIDE 19

RUHR-UNIVERSITÄT BOCHUM

Target

1024-bit HF Register

To evaluate the influence of

  • perating conditions, choose

an instance that leaks a lot: 1024-bit HF Input Register

  • filled either with 0s or 1s
  • average fanout of 11

Q Q

SET CLR

D Q Q

SET CLR

D Q Q

SET CLR

D Q Q

SET CLR

D Q Q

SET CLR

D

... ... ... ... ...

CLK

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 6

slide-20
SLIDE 20

RUHR-UNIVERSITÄT BOCHUM

Target

1024-bit HF Register

To evaluate the influence of

  • perating conditions, choose

an instance that leaks a lot: 1024-bit HF Input Register

  • filled either with 0s or 1s
  • average fanout of 11

Q Q

SET CLR

D Q Q

SET CLR

D Q Q

SET CLR

D Q Q

SET CLR

D Q Q

SET CLR

D

... ... ... ... ...

CLK

Q Q

SET CLR

D Q Q

SET CLR

D Q Q

SET CLR

D Q Q

SET CLR

D Q Q

SET CLR

D

... ... ... ... ...

CLK 1

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 6

slide-21
SLIDE 21

Subsection 1 90 nm ASIC

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 7

slide-22
SLIDE 22

RUHR-UNIVERSITÄT BOCHUM

90 nm ASIC – Normal Operating Conditions

5,000 Measurements at 1.2 V and 20 ◦C

75 80 85 90 95 100 105 110 115

Leakage current [µA]

100 200 300

Frequency of occurrence

11...1 00...0

t

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 8

slide-23
SLIDE 23

RUHR-UNIVERSITÄT BOCHUM

90 nm ASIC – Normal Operating Conditions

5,000 Measurements at 1.2 V and 20 ◦C

75 80 85 90 95 100 105 110 115

Leakage current [µA]

100 200 300

Frequency of occurrence

11...1 00...0

1000 2000 3000 4000 5000

Number of measurements

500 1000 1500 2000

t-statistics

t

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 8

slide-24
SLIDE 24

RUHR-UNIVERSITÄT BOCHUM

90 nm ASIC – Normal Operating Conditions

5,000 Measurements at 1.2 V and 20 ◦C

75 80 85 90 95 100 105 110 115

Leakage current [µA]

100 200 300

Frequency of occurrence

11...1 00...0

1000 2000 3000 4000 5000

Number of measurements

500 1000 1500 2000

t-statistics

Difference of Means 4.1353 µA Average Total Current 96.5 µA

t-value (after 5,000 Traces)

480

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 8

slide-25
SLIDE 25

RUHR-UNIVERSITÄT BOCHUM

90 nm ASIC – Increased Supply Voltage

5,000 Measurements at 1.6 V and 20 ◦C

450 455 460 465 470 475 480 485

Leakage current [µA]

100 200 300

Frequency of occurrence

11...1 00...0

1000 2000 3000 4000 5000

Number of measurements

500 1000 1500 2000

t-statistics

Difference of Means 18.7822 µA

×4.5419 gain

Average Total Current 467.3 µA

×4.8424 gain t-value (after 5,000 Traces)

1938

×4.0375 gain

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 9

slide-26
SLIDE 26

RUHR-UNIVERSITÄT BOCHUM

90 nm ASIC – Increased Temperature

5,000 Measurements at 1.2 V and 90 ◦C

750 755 760 765 770 775 780 785 790

Leakage current [µA]

100

Frequency of occurrence

11...1 00...0

1000 2000 3000 4000 5000

Number of measurements

500 1000 1500 2000

t-statistics

Difference of Means 14.4754 µA

×3.5004 gain

Average Total Current 771.1 µA

×7.9907 gain t-value (after 5,000 Traces)

526

×1.0958 gain

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 10

slide-27
SLIDE 27

RUHR-UNIVERSITÄT BOCHUM

90 nm ASIC – Increased Voltage and Temperature

5,000 Measurements at 1.6 V and 90 ◦C

1850 1855 1860 1865 1870 1875 1880 1885

Leakage current [µA]

100

Frequency of occurrence

11...1 00...0

1000 2000 3000 4000 5000

Number of measurements

500 1000 1500 2000

t-statistics

Difference of Means 32.3217 µA

×7.8160 gain

Average Total Current 1,867.3 µA

×19.3503 gain t-value (after 5,000 Traces)

867

×1.8063 gain

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 11

slide-28
SLIDE 28

Subsection 2 65 nm ASIC

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 12

slide-29
SLIDE 29

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – Normal Operating Conditions

5,000 Measurements at 1.2 V and 20 ◦C

50 100 150 200 250 300 350

Leakage current [µA]

100 200 300

Frequency of occurrence

11...1 00...0

1000 2000 3000 4000 5000

Number of measurements

5000 10000 15000 20000 25000

t-statistics

Difference of Means 38.4927 µA Average Total Current 154.9 µA

t-value (after 5,000 Traces)

4890

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 13

slide-30
SLIDE 30

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – Increased Supply Voltage

5,000 Measurements at 1.6 V and 20 ◦C

300 350 400 450 500 550 600 650 700 750

Leakage current [µA]

100 200 300

Frequency of occurrence

11...1 00...0

1000 2000 3000 4000 5000

Number of measurements

5000 10000 15000 20000 25000

t-statistics

Difference of Means 105.5205 µA

×2.7413 gain

Average Total Current 529.9 µA

×3.4209 gain t-value (after 5,000 Traces)

10570

×2.1616 gain

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 14

slide-31
SLIDE 31

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – Increased Temperature

5,000 Measurements at 1.2 V and 90 ◦C

1350 1400 1450 1500 1550 1600 1650 1700 1750 1800

Leakage current [µA]

100 200

Frequency of occurrence

11...1 00...0

1000 2000 3000 4000 5000

Number of measurements

5000 10000 15000 20000 25000

t-statistics

Difference of Means 263.1579 µA

×6.8366 gain

Average Total Current 1585.1 µA

×10.2331 gain t-value (after 5,000 Traces)

15360

×3.1411 gain

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 15

slide-32
SLIDE 32

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – Increased Voltage and Temperature

5,000 Measurements at 1.6 V and 90 ◦C

2850 2900 2950 3000 3050 3100 3150 3200 3250

Leakage current [µA]

100

Frequency of occurrence

11...1 00...0

1000 2000 3000 4000 5000

Number of measurements

5000 10000 15000 20000 25000

t-statistics

Difference of Means 450.6296 µA

×11.7069 gain

Average Total Current 3067.2 µA

×19.8012 gain t-value (after 5,000 Traces)

17460

×3.5706 gain

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 16

slide-33
SLIDE 33

Section 3 Technology Comparison

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 17

slide-34
SLIDE 34

RUHR-UNIVERSITÄT BOCHUM

Data Dependency of HF-Register – 90 nm vs. 65 nm

5,000 Measurements

Technology Voltage Temp.

  • Diff. of Means
  • Avg. Total Current

90 nm 1.2 V 20 ◦C 4.1353 µA 96.5 µA 90 nm 1.6 V 20 ◦C 18.7822 µA (×4.54) 467.3 µA (×4.84) 90 nm 1.2 V 90 ◦C 14.4754 µA (×3.50) 771.1 µA (×7.99) 90 nm 1.6 V 90 ◦C 32.3217 µA (×7.82) 1,867.3 µA (×19.35) Technology Voltage Temp.

  • Diff. of Means
  • Avg. Total Current

65 nm 1.2 V 20 ◦C 38.4927 µA 154.9 µA 65 nm 1.6 V 20 ◦C 105.5205 µA (×2.74) 529.9 µA (×3.42) 65 nm 1.2 V 90 ◦C 263.1579 µA (×6.84) 1,585.1 µA (×10.23) 65 nm 1.6 V 90 ◦C 450.6296 µA (×11.71) 3,067.2 µA (×19.80)

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 18

slide-35
SLIDE 35

RUHR-UNIVERSITÄT BOCHUM

Data Dependency of PRESENT Core – 90 nm vs. 65 nm

50,000 Measurements at 1.6 V and 90 ◦C

90 nm ASIC:

  • 60
  • 40
  • 20

20 40 60 Leakage Current 200 400 600

  • Frequ. of occur.

fixed random 10000 20000 30000 40000 50000

Number of measurements 20 40 60 t-statistics

65 nm ASIC:

  • 200
  • 150
  • 100
  • 50

50 100 150 200 250 300 Leakage Current 100 200 300 400

  • Frequ. of occur.

fixed random 10000 20000 30000 40000 50000

Number of measurements 100 200 300 t-statistics Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 19

slide-36
SLIDE 36

RUHR-UNIVERSITÄT BOCHUM

Data Dependency of PRESENT Core – 90 nm vs. 65 nm

50,000 Measurements at 1.6 V and 90 ◦C

90 nm ASIC: 65 nm ASIC:

5000 10000 15000 20000 25000 Number of measurements

  • 0.2

0.2 Correlation 5000 10000 15000 20000 25000 Number of measurements

  • 0.5

0.5 Correlation

90 nm 65 nm Difference of Means 9.15 µA 128.46 µA

t-value (after 50,000 Traces)

61.96 242.50 Correlation 0.17 0.43 Measurements to Disclosure 2,180 100

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 20

slide-37
SLIDE 37

Section 4 Masking

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 21

slide-38
SLIDE 38

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – 1 Share in Register (1-bit)

50,000 Measurements at 1.6 V and 90 ◦C

  • 20
  • 15
  • 10
  • 5

5 10 15 20

Leakage Current

500 1000 1500 2000 2500 3000

Frequency of occurrence

1

10000 20000 30000 40000 50000

Number of measurements

100 200 300 400

t-statistics

1st

number of shares 1 detectable leakage at ... 1st-order

t-value (after 50,000 Traces)

372.4

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 22

slide-39
SLIDE 39

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – 2 Shares in Register (1-bit)

50,000 Measurements at 1.6 V and 90 ◦C

  • 30
  • 20
  • 10

10 20 30

Leakage Current

500 1000 1500 2000 2500

Frequency of occurrence

1

10000 20000 30000 40000 50000

Number of measurements

50 100 150 200 250 300 350

t-statistics

1st 2nd

number of shares 1 2 detectable leakage at ... 1st-order 2nd-order

t-value (after 50,000 Traces)

372.4 265.7

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 23

slide-40
SLIDE 40

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – 3 Shares in Register (1-bit)

50,000 Measurements at 1.6 V and 90 ◦C

  • 30
  • 20
  • 10

10 20 30

Leakage Current

500 1000 1500

Frequency of occurrence

1

10000 20000 30000 40000 50000

Number of measurements

20 40 60 80 100

t-statistics

1st 2nd 3rd

number of shares 1 2 3 detectable leakage at ... 1st-order 2nd-order 3rd-order

t-value (after 50,000 Traces)

372.4 265.7 75.25

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 24

slide-41
SLIDE 41

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – 4 Shares in Register (1-bit)

50,000 Measurements at 1.6 V and 90 ◦C

  • 40
  • 30
  • 20
  • 10

10 20 30 40

Leakage Current

500 1000 1500

Frequency of occurrence

1

10000 20000 30000 40000 50000

Number of measurements

10 20 30 40 50 60

t-statistics

1st 2nd 3rd 4th

number of shares 1 2 3 4 detectable leakage at ... 1st-order 2nd-order 3rd-order 4th-order

t-value (after 50,000 Traces)

372.4 265.7 75.25 44.06

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 25

slide-42
SLIDE 42

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – 5 Shares in Register (1-bit)

50,000 Measurements at 1.6 V and 90 ◦C

  • 50
  • 40
  • 30
  • 20
  • 10

10 20 30 40 50

Leakage Current

200 400 600 800 1000 1200

Frequency of occurrence

1

10000 20000 30000 40000 50000

Number of measurements

5 10 15 20 25 30

t-statistics

1st 2nd 3rd 4th 5th

number of shares 1 2 3 4 5 detectable leakage at ... 1st-order 2nd-order 3rd-order 4th-order 5th-order

t-value (after 50,000 Traces)

372.4 265.7 75.25 44.06 22.00

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 26

slide-43
SLIDE 43

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – 5 Shares in Register (1-bit)

50,000 Measurements at 1.6 V and 90 ◦C

  • 50
  • 40
  • 30
  • 20
  • 10

10 20 30 40 50

Leakage Current

200 400 600 800 1000 1200

Frequency of occurrence

1

10000 20000 30000 40000 50000

Number of measurements

5 10 15 20 25 30

t-statistics

1st 2nd 3rd 4th 5th

number of shares 1 2 3 4 5 detectable leakage at ... 1st-order 2nd-order 3rd-order 4th-order 5th-order

t-value (after 50,000 Traces)

372.4 265.7 75.25 44.06 22.00

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 26

slide-44
SLIDE 44

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – 5 Shares in Register (1-bit)

1,000 Measurements at 1.6 V and 90 ◦C

After the first 1,000 Traces the t-test does not indicate detectable leakage in any order (up to 18 shown) even though the distributions are clearly distinguishable:

  • 50
  • 40
  • 30
  • 20
  • 10

10 20 30 40 50

Leakage Current

5 10 15 20 25 30

Frequency of occurrence

1

100 200 300 400 500 600 700 800 900 1000

Number of measurements

2 4 6 8

t-statistics

1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th 17th 18th Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 27

slide-45
SLIDE 45

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – 5 Shares in Register (1-bit)

1,000 Measurements at 1.6 V and 90 ◦C

Order Conversion/Compression:

  • 50
  • 40
  • 30
  • 20
  • 10

10 20 30 40 50 Leakage Current 5 10 15 20 25 30 Frequency of occurrence 1 100 200 300 400 500 600 700 800 900 1000 Number of measurements 5 10 15 20 25 30 t-statistics

χ✷-Test:

  • 50
  • 40
  • 30
  • 20
  • 10

10 20 30 40 50 Leakage Current 5 10 15 20 25 30 Frequency of occurrence 1 100 200 300 400 500 600 700 800 900 1000 Number of measurements 20 40 60 80 100

  • log10(p)

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 28

slide-46
SLIDE 46

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – Detectability of the Leakage

50,000 Measurements at 1.6 V and 90 ◦C

1 2 3 4 5

Number of Shares

500 1000 1500 2000 2500 3000 3500

  • No. of Traces to detect Leakage

regular t-test

  • rder conversion

x2-test

  • Regular t-test indeed

leads to false negatives at higher orders due to the low noise

  • χ✷-test is pessimistic in

low orders

  • Order conversion, resp.

compression, requires manual slicing of the distributions

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 29

slide-47
SLIDE 47

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – DPA on AES Threshold Implementation Core

100,000 Measurements at 1.6 V and 90 ◦C

Third-order DPA using t-test:

  • 15
  • 10
  • 5

5 10 15

Leakage Current

1000 2000 3000 4000

Frequency of occurrence

Sbox Output Bit = 0 Sbox Output Bit = 1

20000 40000 60000 80000 100000

Number of measurements

2 4 6 8 10

t-statistics

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 30

slide-48
SLIDE 48

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – DPA on AES Threshold Implementation Core

100,000 Measurements at 1.6 V and 90 ◦C

Order Conversion/Compression:

  • 15
  • 10
  • 5

5 10 15 Leakage Current 1000 2000 3000 4000 Frequency of occurrence Sbox Output Bit = 0 Sbox Output Bit = 1 20000 40000 60000 80000 100000

Number of measurements 2 4 6 8 10 t-statistics

χ✷-Test:

  • 15
  • 10
  • 5

5 10 15 Leakage Current 1000 2000 3000 4000 Frequency of occurrence Sbox Output Bit = 0 Sbox Output Bit = 1 20000 40000 60000 80000 100000 Number of measurements 10 20 30 40

  • log10(p)

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 31

slide-49
SLIDE 49

RUHR-UNIVERSITÄT BOCHUM

65 nm ASIC – DPA on AES Threshold Implementation Core

200,000 Measurements at 1.6 V and 90 ◦C

  • No. of Traces for successful DPA

regular t-test 19,000

  • rder conversion

21,000

χ✷-test

10,000

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 32

slide-50
SLIDE 50

Section 5 Clock Control

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 33

slide-51
SLIDE 51

RUHR-UNIVERSITÄT BOCHUM

SKINNY: Last Round State Remains in Circuit

  • 250
  • 200
  • 150
  • 100
  • 50

50 100 150 200 250

Leakage Current

50 100 150 200

Frequency of occurrence

fixed random 5000 10000 15000

Number of measurements

  • 0.4
  • 0.2

0.2 0.4

Correlation coefficient Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 34

slide-52
SLIDE 52

RUHR-UNIVERSITÄT BOCHUM

Conclusion

  • The potency of the static power side-channel increases significantly for smaller

CMOS feature sizes

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 35

slide-53
SLIDE 53

RUHR-UNIVERSITÄT BOCHUM

Conclusion

  • The potency of the static power side-channel increases significantly for smaller

CMOS feature sizes

  • Operating conditions can significantly boost the available information through this

side-channel

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 35

slide-54
SLIDE 54

RUHR-UNIVERSITÄT BOCHUM

Conclusion

  • The potency of the static power side-channel increases significantly for smaller

CMOS feature sizes

  • Operating conditions can significantly boost the available information through this

side-channel

  • Due to the low noise level masked implementations should not be analyzed with

moment-based methods and are susceptible with comparably few traces

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 35

slide-55
SLIDE 55

RUHR-UNIVERSITÄT BOCHUM

Conclusion

  • The potency of the static power side-channel increases significantly for smaller

CMOS feature sizes

  • Operating conditions can significantly boost the available information through this

side-channel

  • Due to the low noise level masked implementations should not be analyzed with

moment-based methods and are susceptible with comparably few traces

  • If sensitive intermediates remain in a circuit after cryptographic operations, static

power side-channel attacks without clock control may be performed

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 35

slide-56
SLIDE 56

Thank you for your attention. Any questions?

Thorben Moos | Static Power SCA of Sub-100 nm CMOS ASICs | August 28th, 2019 36