Get to ASICs Faster Get to ASICs Faster A Novel Mixed Signal - PowerPoint PPT Presentation

February 24-26, 2009 Get to ASICs Faster – Get to ASICs Faster A Novel Mixed Signal Design Methodology Dr Greg Tumbush: Tumbush Enterprises Dr. Greg Tumbush: Tumbush Enterprises ON Semiconductor: Gareth Weale, Dustin Griesdorf, , , Alaa El-agha, Marc Matthey, Andreas Drollinger, William Gonnason Self: Holger Meiners Self: Holger Meiners 1

The Presentation Outline The Presentation Outline TUMBUSH ENTERPRISES • The RP1 project challenge • The solution Create an executable spec for: • Architecture development • Design D i • Verification • • Results Results • Conclusion • Questions Q 2 of 20

The Challenge g TUMBUSH ENTERPRISES • Customer Need – RF System to connect two Hearing Aids RF S t t t t H i Aid – Ultra Low Power – a battery at 1V – 400MHz operation (just outside MICS) 400MHz operation (just outside MICS) – Digital Interface to Orela – Streaming Audio connection – Data Rates > 100 kbps • Project History – Taped out on 0 35um AMIS process – Taped out on 0.35um AMIS process – Chip was DOA • We have 4 Months to Tapeout and NO Si! – Many said it could not be done!!! 3 of 20

The solution The solution TUMBUSH ENTERPRISES • The key to the solution is in: 1) Methodology 2) Simplicity 3) 3) Ri k Miti Risk Mitigation ti 4) Methodology! • The shortest path to the end product that provides the lowest risk is the only solution. 4 of 20

Understand where you need to be Understand where you need to be TUMBUSH ENTERPRISES • Customer specifies: Parameter Parameter Spec Spec – What Wh t Current Consumption Less than 1.5mA – But NOT how Range At least 40cm Data Rate At least 128kbps Modulation Binary FSK RF Bandwidth 300kHz 10 -5 Bit Error Rate (BER) Size BTE and ITE aids • Understand the interdependencies up-front – Power vs. Range – Power vs. Data Rate Power vs. Data Rate – Frequency of Operation vs. Size 5 of 20

System Level Design System Level Design TUMBUSH ENTERPRISES • The first task in the design flow is to partition the System y – Clear Interface definitions – Sub-blocks further defined • Analog A l • Digital • Software • Divide and Conquer 6 of 20

ENTERPRISES TUMBUSH 7 of 20 Interface Definitions are CRITICAL Digital Sub-System

Analog RF Front End Analog RF Front End TUMBUSH ENTERPRISES • The analog hierarchy is defined on a block level • First cut simulations based on Excel calculations • Architecture options based upon – Risk Risk – Power – Area Area – Implementation Challenges – Novelty 8 of 20

Analog Architecture Analog Architecture • Quadrature Mixing – low TUMBUSH ENTERPRISES noise • 2x VCO – needed for d d f quadrature (Power risk) • “Simple” design p g A Antenna Subsystem • Filters are challenging 9 of 20

Traditional MS Design Flow Traditional MS Design Flow TUMBUSH ENTERPRISES Serial nature and “long” correction loops kill the correction loops kill the schedule requirement! 10 of 20

Our MS Design Flow Our MS Design Flow High Level Modeling TUMBUSH ENTERPRISES Architecture refinement up front Optimize block level specs Rapid design iteration cycles Executable Spec! Confidence going into the time intensive design phase time intensive design phase Lower risk to GDSII Faster to GDSII 11 of 20

Executable Spec – What is it? Executable Spec What is it? TUMBUSH ENTERPRISES • Complete simulation model of the system including software tools and firmware. ft t l d fi • High level models Reusable! • • Quick architecture exploration/improvements Quick architecture exploration/improvements • SystemC for digital blocks • ADS for analog/RF blocks ADS for analog/RF blocks • Simulation model is spec for Digital/Analog design • System validation can begin as soon as first SystemC/ADS executable spec is complete 12 of 20

What is ADS? What is ADS? TUMBUSH ENTERPRISES • Agilent Advanced Design System • The tool is developed for RFIC design • Uses a graphical layout to create circuits • C Can customize provided elements t i id d l t • Can create your own elements • • Can combine circuit level and behavioral level Can combine circuit level and behavioral level • New versions support SystemC directly – We had to rely on file IO to interface y 13 of 20

SystemC for Digital Design/ Verification TUMBUSH ENTERPRISES • SystemC is golden model of digital function • Cycle or transaction accurate <- Mix in same system • Don’t have to model every facet of system  Reset, Analog I/O R t A l I/O  Separate testbench with analog models <- New Bugs! • • SystemC and RTL are co-simulated SystemC and RTL are co simulated 14 of 20

SystemC and RTL are co-simulated SystemC and RTL are co simulated TUMBUSH ENTERPRISES 128 128 ecc_encoder.cpp I 2 C Clock Control Registers Interface File pass/ pass/ I/O compare fail ECC AD Modulator Encoding Encoder 128 PCM ecc_encoder.vhd ecc encoder vhd Interface 128 AD ECC Demodulator/ Decoding clock recovery Decoder • Fundamentally changes the verification problem! y g p 15 of 20

ADS for Analog Design/ Verification • Derive and verify specs TUMBUSH ENTERPRISES • Examine tradeoffs between blocks • I t Interface with SystemC to verify end-to-end f ith S t C t if d t d performance  Graph shows VCO phase noise curves versus BER (pn @ 1kHz, 10kHz and 100kHz)  A plot normally only possible with post-Si S analysis 16 of 20

Measurement Results Measurement Results TUMBUSH ENTERPRISES Parameter Parameter Requirement Requirement Measured Measured Pass/Fail Pass/Fail Data Rate 128 kbps 128 kbps PASS Transmit Output Power -15dBm -16 dBm OK Receiver Sensitivity -75dBm -85dBm PASS Max BER 10E-3 10E-3 PASS Max Spurious Emission Max Spurious Emission -20dBc (402-405) 20dBc (402 405) < 20dB <-20dB PASS PASS Max Modulation Bandwidth 300kHz@ -20dBc 300 kHz PASS Max Current Consumption 1.5 mA 1.5mA TX 1.6mA RX OK • Audio Pass Through is working well • Range > 2m with matched 50 Ohm Antennas Range > 2m with matched 50 Ohm Antennas • ~ 10 issues to be addressed for final cut!!! 17 of 20

ENTERPRISES TUMBUSH 18 of 20 Si Version i Si V t Cadence Layout RP1 – The die The die L C d RP1

Conclusion Conclusion TUMBUSH • Novel methodology for designing mixed signal systems ENTERPRISES • Create a high level executable specification g p • Leveraged for architecture, design, verification • Architecture to GDSII in less than 4 months • Newest ADS release can directly simulate SystemC. • SystemC synthesis? 19 of 20

Thank You! Thank You! TUMBUSH ENTERPRISES These slides will be at These slides will be at www.tumbush.com/papers/DVCon09 Digital/SystemC questions: g greg@tumbush.com g@ Analog Questions: Alaa.El-Agha@onsemi.com Q Questions? ti ? 20 of 20