Get to ASICs Faster Get to ASICs Faster A Novel Mixed Signal - - PowerPoint PPT Presentation

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Get to ASICs Faster Get to ASICs Faster A Novel Mixed Signal - - PowerPoint PPT Presentation

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February 24-26, 2009 Get to ASICs Faster Get to ASICs Faster A Novel Mixed Signal Design Methodology Dr Greg Tumbush: Tumbush Enterprises Dr. Greg Tumbush: Tumbush Enterprises ON Semiconductor: Gareth Weale, Dustin Griesdorf, , , Alaa

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SLIDE 1

February 24-26, 2009

Get to ASICs Faster – Get to ASICs Faster A Novel Mixed Signal Design Methodology Dr Greg Tumbush: Tumbush Enterprises

ON Semiconductor: Gareth Weale, Dustin Griesdorf,

  • Dr. Greg Tumbush: Tumbush Enterprises

, , Alaa El-agha, Marc Matthey, Andreas Drollinger, William Gonnason Self: Holger Meiners Self: Holger Meiners

1

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SLIDE 2

The Presentation Outline

TUMBUSH

ENTERPRISES

The Presentation Outline

  • The RP1 project challenge
  • The solution
  • Architecture development

D i

Create an executable spec for:

  • Design
  • Verification
  • Results
  • Results
  • Conclusion
  • Questions

Q

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SLIDE 3

The Challenge

TUMBUSH

ENTERPRISES

g

  • Customer Need

RF S t t t t H i Aid

– RF System to connect two Hearing Aids – Ultra Low Power – a battery at 1V – 400MHz operation (just outside MICS)

400MHz operation (just outside MICS)

– Digital Interface to Orela – Streaming Audio connection – Data Rates > 100 kbps

  • Project History

– Taped out on 0 35um AMIS process – Taped out on 0.35um AMIS process – Chip was DOA

  • We have 4 Months to Tapeout and NO Si!

– Many said it could not be done!!!

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SLIDE 4

The solution

TUMBUSH

ENTERPRISES

The solution

  • The key to the solution is in:

1) Methodology 2) Simplicity 3) Ri k Miti ti 3) Risk Mitigation 4) Methodology!

  • The shortest path to the end product that provides the

lowest risk is the only solution.

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SLIDE 5

Understand where you need to be

TUMBUSH

ENTERPRISES

Understand where you need to be

  • Customer specifies:

Wh t

Parameter Spec

– What – But NOT how

Parameter Spec

Current Consumption Less than 1.5mA Range At least 40cm Data Rate At least 128kbps Modulation Binary FSK RF Bandwidth 300kHz Bit Error Rate (BER) 10-5 Size BTE and ITE aids

  • Understand the interdependencies up-front

– Power vs. Range – Power vs. Data Rate Power vs. Data Rate – Frequency of Operation vs. Size

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SLIDE 6

System Level Design

TUMBUSH

ENTERPRISES

System Level Design

  • The first task in the design flow is to partition the

System y – Clear Interface definitions – Sub-blocks further defined

A l

  • Analog
  • Digital
  • Software
  • Divide and Conquer

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SLIDE 7

Digital Sub-System

TUMBUSH

ENTERPRISES

Interface Definitions are CRITICAL

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SLIDE 8

Analog RF Front End

TUMBUSH

ENTERPRISES

Analog RF Front End

  • The analog hierarchy is defined on a block level
  • First cut simulations based on Excel calculations
  • Architecture options based upon

Risk – Risk – Power – Area Area – Implementation Challenges – Novelty

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SLIDE 9

Analog Architecture

TUMBUSH

ENTERPRISES

Analog Architecture

  • Quadrature Mixing – low

noise d d f

  • 2x VCO – needed for

quadrature (Power risk)

  • “Simple” design

A

p g

  • Filters are challenging

Antenna Subsystem 9 of 20

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SLIDE 10

Traditional MS Design Flow

TUMBUSH

ENTERPRISES

Traditional MS Design Flow

Serial nature and “long” correction loops kill the correction loops kill the schedule requirement!

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SLIDE 11

Our MS Design Flow

TUMBUSH

ENTERPRISES

Our MS Design Flow

High Level Modeling

Architecture refinement up front Optimize block level specs Rapid design iteration cycles

Executable Spec!

Confidence going into the time intensive design phase time intensive design phase Lower risk to GDSII Faster to GDSII

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SLIDE 12

Executable Spec – What is it?

TUMBUSH

ENTERPRISES

Executable Spec What is it?

  • Complete simulation model of the system including

ft t l d fi software tools and firmware.

  • High level models
  • Quick architecture exploration/improvements

Reusable!

  • Quick architecture exploration/improvements
  • SystemC for digital blocks
  • ADS for analog/RF blocks

ADS for analog/RF blocks

  • Simulation model is spec for Digital/Analog design
  • System validation can begin as soon as first

SystemC/ADS executable spec is complete

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SLIDE 13

What is ADS?

TUMBUSH

ENTERPRISES

What is ADS?

  • Agilent Advanced Design System
  • The tool is developed for RFIC design
  • Uses a graphical layout to create circuits

C t i id d l t

  • Can customize provided elements
  • Can create your own elements
  • Can combine circuit level and behavioral level
  • Can combine circuit level and behavioral level
  • New versions support SystemC directly

– We had to rely on file IO to interface y

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SLIDE 14

SystemC for Digital

TUMBUSH

ENTERPRISES

Design/ Verification

  • SystemC is golden model of digital function
  • Cycle or transaction accurate
  • Don’t have to model every facet of system

R t A l I/O

<- Mix in same system

  • Reset, Analog I/O
  • Separate testbench with analog models
  • SystemC and RTL are co-simulated

<- New Bugs!

  • SystemC and RTL are co simulated

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SLIDE 15

SystemC and RTL are co-simulated

TUMBUSH

ENTERPRISES

SystemC and RTL are co simulated

Control Registers Clock I2C Interface

ecc_encoder.cpp 128 128

File

pass/

AD Encoder PCM ECC Encoding Modulator

ecc encoder vhd 128

I/O

compare pass/ fail

Interface ECC Decoding Demodulator/ clock recovery AD Decoder

ecc_encoder.vhd 128

  • Fundamentally changes the verification problem!

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y g p

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ADS for Analog Design/ Verification

TUMBUSH

ENTERPRISES

  • Derive and verify specs
  • Examine tradeoffs between blocks

I t f ith S t C t if d t d

  • Interface with SystemC to verify end-to-end

performance

 Graph shows VCO phase noise curves versus BER (pn @ 1kHz, 10kHz and 100kHz)  A plot normally only S possible with post-Si analysis

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SLIDE 17

Measurement Results

TUMBUSH

ENTERPRISES

Measurement Results

Parameter Requirement Measured Pass/Fail Parameter Requirement Measured Pass/Fail Data Rate 128 kbps 128 kbps PASS Transmit Output Power

  • 15dBm
  • 16 dBm

OK Receiver Sensitivity

  • 75dBm
  • 85dBm

PASS Max BER 10E-3 10E-3 PASS Max Spurious Emission 20dBc (402 405) < 20dB PASS Max Spurious Emission

  • 20dBc (402-405)

<-20dB PASS Max Modulation Bandwidth 300kHz@ -20dBc 300 kHz PASS Max Current Consumption 1.5 mA 1.5mA TX 1.6mA RX OK

  • Audio Pass Through is working well
  • Range > 2m with matched 50 Ohm Antennas

Range > 2m with matched 50 Ohm Antennas

  • ~ 10 issues to be addressed for final cut!!!

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SLIDE 18

RP1 – The die

TUMBUSH

ENTERPRISES

RP1 The die

C d L t Si V i Cadence Layout Si Version

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SLIDE 19

Conclusion

TUMBUSH

ENTERPRISES

Conclusion

  • Novel methodology for designing mixed signal systems
  • Create a high level executable specification

g p

  • Leveraged for architecture, design, verification
  • Architecture to GDSII in less than 4 months
  • Newest ADS release can directly simulate SystemC.
  • SystemC synthesis?

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SLIDE 20

Thank You!

TUMBUSH

ENTERPRISES

Thank You!

These slides will be at These slides will be at www.tumbush.com/papers/DVCon09 Digital/SystemC questions: greg@tumbush.com g g@ Analog Questions:

Q ti ?

Alaa.El-Agha@onsemi.com

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Questions?