ECON ASICs Jim Hirschauer, Ralph Wickwire ASICs PMG 11 Nov 2019 - PowerPoint PPT Presentation

ECON ASICs Jim Hirschauer, Ralph Wickwire ASICs PMG 11 Nov 2019

DOE CD-1 IPR and CERN P2UG • CD-1 / IPR went well on Oct 22-24. • Reviewers clearly concerned about ECON: The ECON ASIC is a critical component for which the US has sole responsibility. It was recently redesigned to simplify the chip and in the present schedule is planned to require only a single prototype run prior to the production run. We consider that under any circumstances the availability of the required level of engineering resources should be maintained on the schedule that was presented. This should continue to be the highest priority for the Fermilab ASIC engineering group , as was stated during this review. • Similar conclusion expected from ongoing P2UG review at CERN

ECON-T architecture and block design status • Wickwire has made major updates of ECON-T specification block diagrams and working document. 12 * 12 * 12 *4 * 12 *4 * 2 * 7 * 14 * Various 32b 28b 21b 21b 32b 32b ePortRx + Switch matrix + ’ Calib Algorithms Formatter Bu ff er Word Aligner Float ➔ Fix eTx 40 MHz aligned 1.28 GHz 1.28 GHz data 28 bits per differential differential ePortRx Switch Matrix / Float to Fix Calibration Algorithms Formatter Buffer ePortTx serial channel serial I need to add max 840x16 eports Switch Float to Reg Multiply Reg eports Threshold-Sum Reg Matrix Fix DOUT[1:0][31:0] and minimum bandwidth Size is max possible latency (30 BX) * Dout_p[0] Serial to Channel Parallel Din_p[0] ePortRxDataGroup[0][27:0] FRAMEQ[24:0][15:0] SM[0][0][20:0] SM[0][0]*CALV[0][0] 21 CALQ[0][0][20:0] CALQ[11:0][3:0][20:0] CHARGEQ[47:0][6:0] 28 28 28 4x21 4x21 1 to 25 16 bit words Dout_n[0] parallel aligner to Serial Din_n[0] CALQ[0][1][20:0] Reg SM[0][1][20:0] SM[0][1]*CALV[0][1] 21 used for each algorithm. the max number of output elinks (14 CALQ[0][2][20:0] SM[0][2][20:0] SM[0][2]*CALV[0][2] 21 THRESV[11:0][3:0][20:0] NTCQ[5:0] Dout_p[1] CALQ[0][3][20:0] Default Serial to Channel SM[0][3][20:0] SM[0][3]*CALV[0][3] 21 elinks) * the number of 16 b words per Parallel Din_p[1] ePortRxDataGroup[1][27:0] SM[1][0][20:0] CALQ[1][0][20:0] DATATYPEQ[2:0] 28 SM[1][0]*CALV[1][0] 21 28 28 4x21 4x21 Clock gated if not Dout_n[1] parallel aligner WFRAME_NUMW[4:0] to Serial Din_n[1] CALQ[1][1][20:0] SM[1][1][20:0] SM[1][1]*CALV[1][1] 21 BX per elink (2) = 30*14*2=840 1 to 25 16 bit words SM[1][2][20:0] CALQ[1][2][20:0] ADD_MAP[11:0][3:0] SM[1][2]*CALV[1][2] 21 used DOUT[3:2][31:0] Dout_p[2] Serial to Channel SM[1][3][20:0] CALQ[1][3][20:0] Parallel Din_p[2] SM[1][3]*CALV[1][3] 21 ePortRxDataGroup[2][27:0] MOD_SUM[23:0] (3 third sums) 28 28 28 4x21 4x21 Dout_n[2] parallel aligner to Serial Din_n[2] Dout_p[3] Serial to Channel Parallel Din_p[3] ePortRxDataGroup[3][27:0] 28 28 28 4x21 4x21 Dout_n[3] parallel aligner to Serial Din_n[3] ECON-T: Super Trigger Cell DOUT[5:4][31:0] Dout_p[4] Serial to Channel Parallel Din_p[4] ePortRxDataGroup[4][27:0] CALQ[11:0][3:0][20:0] STC_2X2_SUM[11:0][7:0] 28 28 28 4x21 4x21 Dout_n[4] parallel aligner to Serial Din_n[4] ALG type 1 THREE_SUM[23:0] 840 * 16b Clock gated if not Dout_p[5] Serial to Channel Parallel Din_p[5] ePortRxDataGroup[5][27:0] used 28 28 28 4x21 4x21 Dout_n[5] parallel aligner to Serial Din_n[5] DOUT[7:6][31:0] Dout_p[6] Serial to Channel Parallel Din_p[6] Best Choice ePortRxDataGroup[6][27:0] 28 28 28 4x21 4x21 Dout_n[6] parallel aligner to Serial Din_n[6] CALQ[11:0][3:0][20:0] BC_CHARGE[23:0][7:0] ALG type 2 Dout_p[7] Serial to Channel BC_NUM_OUTPUTS[1:0] BC_bitmap[11:0][3:0] ECON-D: Parallel Din_p[7] ePortRxDataGroup[7][27:0] 28 28 28 4x21 4x21 Clock gated if not Dout_n[7] parallel aligner to Serial Din_n[7] Number of MOD_SUM[23:0] output channels used DOUT[9:8][31:0] is 8, 12, 16 and 24 Dout_p[8] Serial to Channel ePortRxDataGroup[8][27:0] Parallel Din_p[8] 10k * 16b 28 28 28 4x21 4x21 Dout_n[8] parallel aligner to Serial Din_n[8] Repeater / eTx Dout_p[9] Serial to Channel CALQ[11:0][3:0][20:0] Training REPEATERQ[11:0][3:0][6:0] Parallel Din_p[9] ePortRxDataGroup[9][27:0] 28 28 28 4x21 4x21 Dout_n[9] parallel aligner ALG type 3 to Serial Din_n[9] Clock gated if not DOUT[11:10][31:0] Dout_p[10] Serial to Channel Parallel Din_p[10] ePortRxDataGroup[10][27:0] used 28 28 28 4x21 4x21 Dout_n[10] parallel aligner to Serial Din_n[10] SM[11][0][20:0] SM[11][0]*CALV[11][0] 21 CALQ[11][0][20:0] SM[11][1][20:0] SM[11][1]*CALV[11][1] Dout_p[11] Serial to Channel 21 CALQ[11][1][20:0] Parallel Din_p[11] ePortRxDataGroup[11][27:0] SM[11][2][20:0] SM[11][2]*CALV[11][2] 21 CALQ[11][2][20:0] 28 28 28 4x21 4x21 Dout_n[11] parallel aligner to Serial Din_n[11] SM[11][3][20:0] SM[11][3]*CALV[11][3] 21 CALQ[11][3][20:0] DOUT[13:12][31:0] Dout_p[12] Parallel BX_counter[4:0] HEADER[4:0] Aligner 5 5 Dout_n[12] to Serial Dout_p[13] Parallel Dout_n[13] to Serial Clk40 40MHz CLK W POINTER CONTROL Range is TBD) from I2C registers Hirschauer – Decimal point IE 1.28 GHz Number of output channels is 8, (Float - Significant bits TBD by Hirschauer) from I2C registers (Significant bits TBD by 0 is default – threshold/sum Write pointer control CALV[11:0][3:0][6:0] EPORTRX_NOT_USED[2:0] EPORTTX_NOT_USED[2:0] THRESV[11:0][3:0][6:0] BC_NUM_OUTPUTS[1:0] The pointer control needs to keep track ALGORITHM_TYPE[1:0] ALGORITHM_TYPE[1:0] Rx WA MUX FF Cal Th BC STC Frmttr Buffer eTx I2C register value of how many 16 bit words are written, 2 erx at a time 12, 16 and 24 2 etx at a time 3 – Repeater & how many are read (always 2xNTx per 1 – STC 2 – BC 40 MHz cycle, in the case of the case of Latency control the FIFO buffer), fill in fake data when Layout Layout Layout Layout Layout Layout there is an underrun. The EConT spec has a method to take care of underrun EPORTRX_NOT_USED[2:0] by using the last frame with the same 2 erx at a time Synth Synthe Synthe Synthe Synthe Synthe esis sis sis sis sis sis RTL + RTL + RTL + RTL + RTL + RTL + – → sim sim sim sim sim sim Ralph Ralph Ralph Sandeep LLR/Split Hammer Braga Hammer Ralph – → → 840 – 16 – → – → – → → – → →

Verification • Verification team : Hoff, Gingu + Noonan, Ghosh, Kwok • Steady progress on UVM test benches and test data: Test bench Modules included Test bench status Test data status Not started -targeting March TB1 Full chip complete TB2 i2c complete N/A TB3 ePortRx + Word Aligner In progress N/A TB4 MUX + Flt ➔ Fix + Calib complete complete threshold : complete TB5 Algorithms In progress best choice : complete STC : in progress TB6 Formatter + Buffer Not started complete

Best choice algorithm optimization • L. Pacheco, T. Romanteau, J.B.Sauvan (LLR) have written Best Choice algorithm RTL • D. Č oko, A. Kristi ć , J. Musi ć , J. O ž egovi ć , I. Puljak (University of Split - FESB) have synthesized and tested • Recently studied design optimization for power, area, simplicity in 4 parameters: • Maximum number of selectable TC : 23 or 48 • Sorting compressed (7b) or uncompressed (18b) TC • Pipeline : 0-stage (1BX latency) or 1-stage (2BX latency) • Clock speed : 40 or 160 MHz • Simplest design • 48 TC + 18b sort + 0-stage pipeline + 40 MHz clock has acceptable • Acceptable : 30k gates, 0.14 mm 2 , 0.15 mW/channel • Power/area optimized design • 23 TC + 7b sort + 0-stage pipeline + 160 MHz clock : • 6k gates, 0.03 mm 2 area, 0.02 mW/channel Will request Split+LLR to continue with simplest design.

1.28 Gbps transmitter • Reported last time that Davide Braga started work on 1.28 Gbps serializer. • Unfortunately, no progress and only 14 hours of effort from in 3 weeks since last PMG (Oct 14 - Nov 4). • Also recently learned that Davide is unable to work on ECON in November. • New milestone : complete new 1.28 Gbps serializer (to use with lpGBT line driver) by 20- DEC-2019.

1.28 Gbps receiver • Sandeep returned from leave on Oct 21. • ECON received 20 hours of Sandeep's effort in 2 weeks since (Oct 21 - Nov 4). • Better than nothing, but not sufficient over long term. • Recent progress : ePortRx analog and digital blocks reviewed, understood, and plan formed • Next steps with dates from Sep ASICs PMG and new dates: Step Previous date New date Strip unneeded RTL from lpGBT ePortRx digital blocks Sep 15 Nov 15 Simulate ePortRx (analog + modified RTL) + ECON Word Aligner Oct 1 Nov 26 Incorporate eRx pad block with ePortRx + Word Aligner Oct 15 ? Complete synthesis, triplication, and layout Dec 15 Feb 15?

Milestones (1) from Oct 14 × × × × × × × � 8

Milestones (1) × × × Expect 2 month delay � 9

Milestones (2) � 10

Status Matrix - Oct 14 � 11

Status Matrix - Nov 11 • Completed : 12.5 person-weeks (3.1 FTE) • Obseleted : 20.6 person-weeks • Added : 28.2 person-weeks � 12 • Net : 4.9 person-weeks ahead

Additional material � 13