ECON ASICs Jim Hirschauer, Ralph Wickwire ASICs PMG 11 Nov 2019 - - PowerPoint PPT Presentation

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ECON ASICs Jim Hirschauer, Ralph Wickwire ASICs PMG 11 Nov 2019 - - PowerPoint PPT Presentation

Sep 10, 2022 217 likes •378 views

ECON ASICs Jim Hirschauer, Ralph Wickwire ASICs PMG 11 Nov 2019 DOE CD-1 IPR and CERN P2UG CD-1 / IPR went well on Oct 22-24. Reviewers clearly concerned about ECON: The ECON ASIC is a critical component for which the US has sole

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SLIDE 1

ECON ASICs

ASICs PMG

11 Nov 2019

Jim Hirschauer, Ralph Wickwire

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SLIDE 2

DOE CD-1 IPR and CERN P2UG

  • CD-1 / IPR went well on Oct 22-24.
  • Reviewers clearly concerned about ECON:

The ECON ASIC is a critical component for which the US has sole responsibility. It was recently redesigned to simplify the chip and in the present schedule is planned to require only a single prototype run prior to the production run. We consider that under any circumstances the availability of the required level of engineering resources should be maintained on the schedule that was presented. This should continue to be the highest priority for the Fermilab ASIC engineering group, as was stated during this review.

  • Similar conclusion expected from ongoing P2UG review at CERN
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SLIDE 3

ECON-T architecture and block design status

  • Wickwire has made major updates of ECON-T specification block diagrams

and working document.

ePortRx

1.28 GHz differential serial eports Din_p[0] Din_n[0] Din_p[1] Din_n[1] Din_p[2] Din_n[2] Din_p[3] Din_n[3] Din_p[4] Din_n[4] Din_p[5] Din_n[5] Din_p[6] Din_n[6] Din_p[7] Din_n[7] Din_p[8] Din_n[8] Din_p[9] Din_n[9] Din_p[10] Din_n[10] Din_p[11] Din_n[11] Serial to parallel Serial to parallel Serial to parallel Serial to parallel Serial to parallel Serial to parallel Serial to parallel Serial to parallel Serial to parallel Serial to parallel Serial to parallel Serial to parallel Channel aligner Channel aligner Channel aligner Channel aligner Channel aligner Channel aligner Channel aligner Channel aligner Channel aligner Channel aligner Channel aligner Channel aligner Aligner 40 MHz aligned data 28 bits per channel ePortRxDataGroup[0][27:0] ePortRxDataGroup[1][27:0] ePortRxDataGroup[2][27:0] ePortRxDataGroup[3][27:0] ePortRxDataGroup[4][27:0] ePortRxDataGroup[5][27:0] ePortRxDataGroup[6][27:0] ePortRxDataGroup[7][27:0] ePortRxDataGroup[8][27:0] ePortRxDataGroup[9][27:0] ePortRxDataGroup[10][27:0] ePortRxDataGroup[11][27:0] BX_counter[4:0]

Switch Matrix / Float to Fix

Switch Matrix 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 Float to Fix Reg 28 4x21 4x21 28 4x21 4x21 28 4x21 4x21 28 4x21 4x21 28 4x21 4x21 28 4x21 4x21 28 4x21 4x21 28 4x21 4x21 28 4x21 4x21 28 4x21 4x21 28 4x21 4x21 28 4x21 4x21 5 SM[0][0][20:0] SM[0][1][20:0] SM[0][2][20:0] SM[0][3][20:0]

Calibration

Multiply SM[0][0]*CALV[0][0] SM[0][1]*CALV[0][1] SM[0][2]*CALV[0][2] SM[0][3]*CALV[0][3] SM[1][0][20:0] SM[1][1][20:0] SM[1][2][20:0] SM[1][3][20:0] SM[1][0]*CALV[1][0] SM[1][1]*CALV[1][1] SM[1][2]*CALV[1][2] SM[1][3]*CALV[1][3] CALV[11:0][3:0][6:0] (Significant bits TBD by Hirschauer – Decimal point IE Range is TBD) from I2C registers Reg 5 21 21 21 21 21 21 21 21

Algorithms

CALQ[0][0][20:0] CALQ[0][1][20:0] CALQ[0][2][20:0] CALQ[0][3][20:0] CALQ[1][0][20:0] CALQ[1][1][20:0] CALQ[1][2][20:0] CALQ[1][3][20:0] Threshold-Sum Default Clock gated if not used SM[11][0][20:0] SM[11][1][20:0] SM[11][2][20:0] SM[11][3][20:0] SM[11][1]*CALV[11][1] SM[11][2]*CALV[11][2] SM[11][3]*CALV[11][3] 21 21 21 21 SM[11][0]*CALV[11][0] CALQ[11][0][20:0] CALQ[11][1][20:0] CALQ[11][2][20:0] CALQ[11][3][20:0] CALQ[11:0][3:0][20:0] THRESV[11:0][3:0][6:0] (Float - Significant bits TBD by Hirschauer) from I2C registers THRESV[11:0][3:0][20:0] CHARGEQ[47:0][6:0] NTCQ[5:0] DATATYPEQ[2:0] ADD_MAP[11:0][3:0] MOD_SUM[23:0] (3 third sums) Reg Super Trigger Cell ALG type 1 Clock gated if not used CALQ[11:0][3:0][20:0] HEADER[4:0] STC_2X2_SUM[11:0][7:0] Best Choice ALG type 2 Clock gated if not used THREE_SUM[23:0] CALQ[11:0][3:0][20:0] Repeater / eTx Training ALG type 3 Clock gated if not used CALQ[11:0][3:0][20:0] REPEATERQ[11:0][3:0][6:0] BC_CHARGE[23:0][7:0] BC_bitmap[11:0][3:0] BC_NUM_OUTPUTS[1:0] Number of
  • utput channels
is 8, 12, 16 and 24 BC_NUM_OUTPUTS[1:0] Number of output channels is 8, 12, 16 and 24

Formatter I need to add max and minimum bandwidth used for each algorithm.

Reg

Buffer 840x16 Size is max possible latency (30 BX) * the max number of output elinks (14 elinks) * the number of 16 b words per BX per elink (2) = 30*14*2=840

FRAMEQ[24:0][15:0] 1 to 25 16 bit words WFRAME_NUMW[4:0] 1 to 25 16 bit words EPORTRX_NOT_USED[2:0] 2 erx at a time EPORTTX_NOT_USED[2:0] 2 etx at a time

W POINTER CONTROL The pointer control needs to keep track

  • f how many 16 bit words are written,

how many are read (always 2xNTx per 40 MHz cycle, in the case of the case of the FIFO buffer), fill in fake data when there is an underrun. The EConT spec has a method to take care of underrun by using the last frame with the same

ALGORITHM_TYPE[1:0] 0 is default – threshold/sum 1 – STC 2 – BC 3 – Repeater I2C register value

ePortTx

1.28 GHz differential serial eports Dout_p[0] Dout_n[0] Dout_p[1] Dout_n[1] Dout_p[2] Dout_n[2] Dout_p[3] Dout_n[3] Dout_p[4] Dout_n[4] Dout_p[5] Dout_n[5] Dout_p[6] Dout_n[6] Dout_p[7] Dout_n[7] Dout_p[8] Dout_n[8] Dout_p[9] Dout_n[9] Dout_p[10] Dout_n[10] Dout_p[11] Dout_n[11] Parallel to Serial Parallel to Serial Parallel to Serial Parallel to Serial Parallel to Serial Parallel to Serial Parallel to Serial Parallel to Serial Parallel to Serial Parallel to Serial Parallel to Serial Parallel to Serial DOUT[1:0][31:0] DOUT[3:2][31:0] DOUT[5:4][31:0] DOUT[7:6][31:0] DOUT[9:8][31:0] DOUT[11:10][31:0] Dout_p[12] Dout_n[12] Parallel to Serial Dout_p[13] Dout_n[13] Parallel to Serial DOUT[13:12][31:0] –→ → –→ –→ → –→ –→ → –→ Clk40 1.28 GHz ’ MOD_SUM[23:0] EPORTRX_NOT_USED[2:0] 2 erx at a time ALGORITHM_TYPE[1:0]

840 – 16

ePortRx + Word Aligner 12 * 32b 12 * 28b Switch matrix + Float ➔ Fix 12 *4 * 21b Calib 12 *4 * 21b Algorithms Formatter Various Buffer ECON-T: 840 * 16b ECON-D: 10k * 16b eTx 14 * 32b 2 * 7 * 32b Write pointer control & Latency control 40MHz CLK

Rx WA Layout Synth esis RTL + sim MUX FF Cal Layout Synthe sis RTL + sim Th BC STC Layout Synthe sis RTL + sim Buffer Layout Synthe sis RTL + sim Frmttr Layout Synthe sis RTL + sim eTx Layout Synthe sis RTL + sim

Sandeep Ralph Ralph LLR/Split Ralph Ralph Hammer Hammer Braga

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SLIDE 4

Verification

  • Verification team : Hoff, Gingu + Noonan, Ghosh, Kwok
  • Steady progress on UVM test benches and test data:

Test bench Modules included Test bench status Test data status TB1 Full chip Not started -targeting March complete TB2 i2c complete N/A TB3 ePortRx + Word Aligner In progress N/A TB4 MUX + Flt➔Fix + Calib complete complete TB5 Algorithms In progress threshold : complete best choice : complete STC : in progress TB6 Formatter + Buffer Not started complete

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SLIDE 5

Best choice algorithm optimization

  • L. Pacheco, T. Romanteau, J.B.Sauvan (LLR) have written Best Choice algorithm RTL
  • D. Čoko, A. Kristić, J. Musić, J. Ožegović, I. Puljak (University of Split - FESB) have synthesized and tested
  • Recently studied design optimization for power, area, simplicity in 4 parameters:
  • Maximum number of selectable TC: 23 or 48
  • Sorting compressed (7b) or uncompressed (18b) TC
  • Pipeline : 0-stage (1BX latency) or 1-stage (2BX latency)
  • Clock speed : 40 or 160 MHz
  • Simplest design
  • 48 TC + 18b sort + 0-stage pipeline + 40 MHz clock has acceptable
  • Acceptable : 30k gates, 0.14 mm2, 0.15 mW/channel
  • Power/area optimized design
  • 23 TC + 7b sort + 0-stage pipeline + 160 MHz clock :
  • 6k gates, 0.03 mm2 area, 0.02 mW/channel

Will request Split+LLR to continue with simplest design.

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SLIDE 6

1.28 Gbps transmitter

  • Reported last time that Davide Braga started work on 1.28 Gbps serializer.
  • Unfortunately, no progress and only 14 hours of effort from in 3 weeks since last

PMG (Oct 14 - Nov 4).

  • Also recently learned that Davide is unable to work on ECON in November.
  • New milestone: complete new 1.28 Gbps serializer (to use with lpGBT line driver) by 20-

DEC-2019.

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SLIDE 7

1.28 Gbps receiver

  • Sandeep returned from leave on Oct 21.
  • ECON received 20 hours of Sandeep's effort in 2 weeks since (Oct 21 - Nov 4).
  • Better than nothing, but not sufficient over long term.
  • Recent progress : ePortRx analog and digital blocks reviewed, understood, and plan formed
  • Next steps with dates from Sep ASICs PMG and new dates:

Step Previous date New date Strip unneeded RTL from lpGBT ePortRx digital blocks Sep 15 Nov 15 Simulate ePortRx (analog + modified RTL) + ECON Word Aligner Oct 1 Nov 26 Incorporate eRx pad block with ePortRx + Word Aligner Oct 15 ? Complete synthesis, triplication, and layout Dec 15 Feb 15?

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SLIDE 8

8

Milestones (1) from Oct 14

× × × × × × ×

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SLIDE 9

9

Milestones (1)

× × ×

Expect 2 month delay

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SLIDE 10

10

Milestones (2)

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SLIDE 11

11

Status Matrix - Oct 14

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SLIDE 12

12

Status Matrix - Nov 11

  • Completed : 12.5 person-weeks (3.1 FTE)
  • Obseleted : 20.6 person-weeks
  • Added : 28.2 person-weeks
  • Net : 4.9 person-weeks ahead
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SLIDE 13

13

Additional material

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SLIDE 14

Team summary

  • Hirschauer (50%) : 15+ yrs HEP / 5+ yrs Upgrade Coordination experience
  • Co-coordinator: specification, ASIC and system architecture
  • Ralph (100%) : 15+ yrs digital experience in ASIC industry
  • Co-coordinator: specification, ASIC architecture, top-level chip integration, RTL for some blocks
  • Rubinov (20%) : 20+ yrs system/PCB/FPGA experience & HGCAL system design
  • Specification, ASIC and system architecture
  • Sandeep (60%) : 5+ yrs digital design experience
  • Coordinate implementation (RTL ➔ physical design) and integrate lpGBT 1.28 Gbps receivers
  • Davide (40%) : 10+ years of mixed signals design experience
  • Design 1.28 Gbps transmitters and integrate lpGBT PLL
  • Mike (40%) : 40 years digital design experience
  • RTL for various blocks and implementation
  • Hofg (80%) : 20+ yrs digital design and verification experience
  • Coordinate verification
  • Cristian (60%) : 20+ yrs verilog/HDL experience
  • Verification
  • Alpana (30%): 10+ yrs in ASIC design support
  • Tools support, RTL, implementation, and verification
  • University of Split /FESB, Croatia: 3 elec eng faculty with verilog and synthesis experience
  • RTL for ECON algorithms
  • LLR, Paris : Electrical engineer and physicist with verilog experience
  • RTL for ECON algorithms
  • FNAL, Florida Tech University, Northwestern University : Scientist, 2 post docs, 2-4 students
  • Specification and verification

Color code

  • ASIC design
  • Verification
  • External RTL design
  • Specification, architecture,

support