ECON ASICs Gregory Deptuch, Zoltan Gecse, Jim Hirschauer, Sandeep - - PowerPoint PPT Presentation

ECON ASICs

ASICs PMG

10 May 2019

Gregory Deptuch, Zoltan Gecse, Jim Hirschauer, Sandeep Miryala, Paul Rubinov

Reminders

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• Two Endcap Concentrator (ECON) ASICs on independent data paths:
• ECON-TRG : select and compress interesting data for transmission off detector at 40 MHz.
• ECON-DAQ : perform zero suppression and concentrate for events passing L1 trigger at 750 kHz.
• Baseline architecture :
• ECON-T : 36x 1.28 Gbps inputs + 3x 10.24 Gbps inputs
• ECON-D : 36x 1.28 Gbps inputs + 7x 1.28 Gbps inputs
• Baseline schedule :
• ECON prototype 1 :
• verify essentially all ECON pieces except internal algorithms including high speed I/O,

power distribution, PCB/package interface, etc.

• ECON prototype 2 :
• incorporate trigger algorithm for ECON-T
• incorporate zero suppression logic and smart buffer for ECON-D
• Need to submit by June 2020 to be ready for full system test
• ECON production : full production of both ECON-T and and ECON-D

Recent developments

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• CD-1 Director's Review
• Comment : We are worried that, as currently envisioned, the first prototype of the ECON concentrator ASIC will

take much longer to design than anticipated and will still have a significant risk of failure. We believe it would be safer to first design a prototype with 36 1.28 Gbps inputs and 7 1.28 Gbps outputs. This is the configuration required for ECON-D, and this configuration could also be used for ECON-T, albeit at the cost of a more complex printed circuit board design requiring more LpGBTs.

• Recommendation : Consider the approach described above for the ECON ASICs to reduce schedule and

performance risks. 


• Optimization of motherboard / system design:
• CMS has been become more concerned about high multiplicity of motherboard variants.
• System design options that reduce motherboard variety impact optimal ECON design.
• ECON schedule:
• Despite excellent progress, latest forecast shows ECON P1 submission moving from Aug ➔ Dec 2019.

Evolving ECON plan* must address all of these developments.

* all plans are necessarily evolving plans

ECON internal mini-review on May 14

4 Goals:

• Finalize ECON architecture choices.
• Present status and plans for ECON

design in more technical detail than possible during usual HGCAL meetings. ECON presenters

• Gregory, Sandeep, Ralph Wickwire, Mike

Hammer (ANL), Ante Kristic (Split), Paul Rubinov, Hirschauer Reviewers:

• Magnus Hansen (CMS electronics

coordinator), Paolo Moreira and Szymon Kulis (lpGBT designers)

• HGCAL people : Paul Aspell, Sandro, etc.

Optimization of motherboard / system design

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• Modules (yellow/green on right) in each 60° sector of

each layer are connected and readout by motherboards (gray on right).

• Modules hold HGCROCs
• Motherboards hold ECONs, optical transmitter(s), etc.
• With 51 layers of varying module arrangement and

varying required bandwidth, the tendency towards a high multiplicity of motherboard variants is evident.

• Minimization of this multiplicity is one

contribution to multi-dimensional

• ptimization

6 12/12 12/12 6/12 12/12 12/12 6/12 Total: 30/36 T V L # DAQ/TRG elinks Maximal concentration 36x1G in (3/1)x10G out Staged compression +serialization 12x1G in 12x1G out

System design : illustration of two approaches

V L L L L D T engine motherboard engine few varieties of complex ECON boards few varieties of complex transmitter boards many varieties of simple passive connection boards D T D T D

7 Maximal concentration 36x1G in (3/1)x10G out Staged compression+serialization 12x1G in 12x1G out

Advantages / Disadvantages of two approaches

Advantages Disadvantages

• Simpler 2-chip engine
• More dense 4-chip engine
• Less flexible load balancing
• more flexible load balancing
• transmitter redundancy
• ~20% lower power
• Longer ECON design time
• Higher risk of ECON

prototype problems

• Single point failure
• More naturally allows isolation of complexity into
• ECON board
• Transmitter board
• Naturally accommodates FPGA ECON emulator board

for system early prototyping

• Less ECON design time
• More unified ECON-D / ECON-T architectures
• Lower risk of ECON prototype problems
• Simpler / less expensive ECON package
• decentralization lowers single point failure risk

ECON development schedules for two approaches

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• Compare schedules for 12in-12out and 36in-(3/1)out

ST ST FC FC ST CMS need-by dates for System Test and Final chip

• Conclusion 12in-12out plan allows for delivery ~6 months sooner than 36in-(3/1)out

Message for ECON May 14 review

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• In the past weeks, Fermilab ECON designers and system designers have considered the diverse

aspects of ECON and HGCAL system design optimization including:

• System / PCB complexity (and associated schedule risks, technical risks, and cost)
• ASIC and package complexity (and associated schedule risks, technical risks, and cost)
• power requirements
• link counts (which drives cost)
• readout redundancy and flexibility
• ease of system prototyping
• Taken all together, we conclude that the 12in-12out ECON design with the associated modular

system design offers more advantages than an 36in-(3/1)out ECON design, so we propose to pursue the 12in-12out design.

To do for May 14 and May 20 P2UG

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• JH : finalize link count comparison
• JH : update power estimates
• JH & GD : provide CMS with intermediate ECON design milestones for Sep 2019 and Jan 2020
• All : finalize talks (drafts have already been reviewed)