[PPT] - Chapter 5 Fundamental parameters The CMOS Inverter for digital PowerPoint Presentation

SLIDE 1

1 Digital IC-Design

Chapter 5 The CMOS Inverter

Digital IC-Design

Fundamental parameters for digital gates

Goal With This Chapter

Analyze Fundamental Parameters

A general understanding of the inverter behavior is useful to understand more complex behavior is useful to understand more complex functions

Outline

Noise Reliability P f Performance Power Consumption

Robustness

Noise - “unwanted variations of voltages and currents in logical nodes” g Classical noise such as thermal and flicker noise are not critical in digital design Noise sources in digital circuits are

Capacitive coupling Capacitive coupling Inductive coupling Power and ground noise

SLIDE 2

2 Capacitive and Inductive Coupling

C V

A voltage or a current change may influence th i l ll l

CCoupling V I Mutual

the signal on a parallel wire, especially when:

Long wires Sub micron tech. Many metal layers

Mutual Inductance I

Power and Ground Noise VDD

A big problem on large

ISwitch

VDD

V VDD RWire

large synchronously clocked chips On chip decoupling capacitors helps Conclusion: The world is not digital. We need to know the limitations p p (≈ 1/10 of the switched C)

Definitions DC Operation Noise Margins Fan OUT - Fan IN DC Operation

Voltage Transfer Characteristic (VTC)

V

5

VOUT VIN

Switching Threshold VM when VIN = VOUT Balanced if VM = VDD/2

VOUT

VOH

2 3 4

VM Vout = VIN

Logical “1” at VOH Logical “0” at VOL

1 2 3 4 5

VIN

1

VOL

SLIDE 3

3 Analog versus Digital Signals

VOH, VOL = nominal t t lt

VOUT

VOH

5

utput voltage

VIH, VIL = acceptable input voltage

VOH

2 3 4

Slope = -1

1 2 3 4

VIN

1

VOL VIH VIL

The noise margins

Accepteble Input Levels Nominal Output Levels

Analog versus Digital Signals

The noise margins are defined as the difference between VOH/VOL and VIH/VIL NM = V

VO

VOH

Undefined Region

VIH NMH

NML = VIL VOL NMH = VOH - VIH

VOL VIL NML

Fan-In and Fan-Out

Fan-in = M Fan-out = N Fan-in = The Fan-out = The number of inputs to the gate number of gates that loads the gate

The Ideal Gate R =∞

VOUT

Rin=∞ Rout=0 Noise Margin=VDD/2 Gain = ∞

VIN

SLIDE 4

4

5

NML = VIL - VOL = 0.75 - 0.50 = 0.25V

A Real Gate

VOUT

2 3 4

VOH VM VIL

NMH = VOH - VIH = 3.50 - 2.25 = 1.25V VM = 1.75V VDD

1 2 3 4 5

VOL

VIN

1

VIH

GND

Dynamic Definitions

Propagation delay Propagation delay Rise and fall time Power consumption

Delay Definitions

VIN

2 t t t

pLH pHL p

+ =

VOUT t 50% tpLH tpHL 90% t 50% tf tr 10%

Ring Oscillator – minimum tp

Odd # of

V5 V4 V3 V2 V1

Odd # of inverters “De-facto Standard” for performance

V1 V3 V2

Fan-out = 1

t

V5 2 N tp V2

SLIDE 5

5 Ring Oscillator

Do tp = 100ps mean 10 GHz chip? Good Custom Design ≈ 1/10 Synthesized design ≈ 1/50 - 1/100 Why? Low load

V5 V4 V3 V2 V1

Low load

Short Wires Fan-out = 1 Low complexity

Power Dissipation

Two measures are important Peak power (Sets wire dimensions) Peak power (Sets wire dimensions) Average power (Battery and cooling)

max peak DD DD

P V i = × ( )

T DD av DD

V P i t dt T =

∫

Power-Delay Product

( ) PDP t P J

Energy per operation

( )

p av

PDP t P J = ×

Energy per switching event

Digital IC-Design

The CMOS Inverter

SLIDE 6

6 Inverters

On-chip resistors are large St ti ti

VDD

Static power consumption VOL ≠ 0 Large tpLH

VDD GND

Extra process step

GND

Extra process step Static power consumption VOL ≠ 0 Large tpLH

The CMOS Inverter

+ Lower static power ti

VDD

consumption + VOH = VDD; VOL = 0 + tpLH = tpHL If properly designed + Low Impedance connection to ground and VDD

More fab. stages
Lower hole mobility

GND

The CMOS Inverter

VDD

Shared power and ground

GND

VDD VDD

Cascaded Abuted cells

Out GND In Out GND In

The CMOS Inverter

VDD

Wider PMOS to compensate for lower mobility

GND

lower mobility

VDD VDD Out GND In Out GND In

SLIDE 7

7 CMOS Inverter - Model

Complementary i.e. output have always a low impedance

R

VDD

y p connection to GND or VDD VOH = VDD VOL = 0

CL R Req-p

VM = f(Req-n, Req-p) VM = VDD/2 if Req-n = Req-p

Req-n

CMOS Static Behavior

Load characteristics Load characteristics VTC Switching threshold Noise margin g

Load Lines

N-channel P-channel

ID

VGS=5V VGS=4V

VDS ID

VGS=-4V VGS=-3V

VDS

VGS=3V

GS

VGS=-5V

Inverter Load Characteristics

ID IDn = -IDp V V V

VGS=5V

The VTC can be determined graphically

IDn

VGS=5V Vin=0V

IDp

VDS Vin = VDD-VGSp

VGS=3V VGS=4V VGS=-3V

Vout= V

DD-VDSp

VDS

VGS=3V VGS=4V Vin=2V Vin=1V VGS=-5V VGS=-4V

Vin = VDD-VGSp Vout = VDD-VDSp

ut

DD DSp

SLIDE 8

8 Inverter Load Characteristics

I

Vin=5V Vin=0V Vin=3V

in

Vin=4V

in

Vin=2V Vin=1V

Vout

Vin=2V Vin=3V VM

Region: Linear - Saturation

V

5

N off N sat

I

Vin=5V Vin=0V

VOUT

2 3 4

N sat P sat N off P lin N sat P lin

Vout

Vin=3V Vin=4V Vin=2V Vin=1V Vin=2V Vin=3V VM

1 2 3 4 5

VIN

1

N lin P off N lin P sat

CMOS Inverter VTC

VTC graphically extracted from the l d li

5

load lines

High noise margin

NMH=VOH-VIH ≈ 5-2.9 = 2.1V NML =VIL-VOL ≈ 2.1-0 = 2.1V

VOUT

VOH= VDD

2 3 4

VM= VDD/2

1 2 3 4 5

VIN

1

VOL= 0

Switching Threshold Both transistors are saturated Long Channel Transistors

2 2

( ) ( ( ) ) 2 2 ( ) ( )

p n M Tn M DD Tp p M Tn M DD Tp n

k k V V V V V k V V V V V k V V V V V − = − − − − ⇒ − = − − + + ⇒ ( ) ( ) 1

M M Tn DD Tp Tn DD Tp p M n

V r V V r V V V r V V k V with r r k + × = + × + ⇒ + + − ⇒ = = +

SLIDE 9

9 Switching Threshold

( ) 1

DD Tp Tn p M n

r V V V k V with r r k + + − = = +

(VTn = -VTp = 0.5 V)

Long Channel Transistors

VM

2 3 4 5

VM

2 3 4 5 1 6 4 8 10

kp/kn

1 2 1 0.1 1 0.32 3.2 10

kp/kn

Wp≈3Wn Switching Threshold

5

( ) 1

DD Tp Tn p M n

r V V V k V with r r k + + − = = + VM

2 3 4

Moderate deviation from kp/kn = 1 gives only small changes in VM W 2W t

1 0.1 1 0.32 3.2 10

kp/kn

Wp = 2Wn common to save area, since the change in VM is small

Switching Threshold: Example

Inverter with W/L = 0.6 μ / 0.35 μ VTn = 0.50, kn = 300 μ, VTp = - 0.65, kp = -103 μ

103 0.59 300

p n

k r k μ μ − = = = ( ) 1

DD Tp Tn M

r V V V V r + + = = +

VDD = 3V

1 0.59 (3 0.65) 0.5 1.18 1 0.59 r V + − + = +

GND

2.5

Balanced 0.25μm inverter

Simulated VTC: Short Channel

1 1.5 2

Vout(V)

0.5 1 1.5 2 2.5 0.5

Vin (V)

SLIDE 10

10

Minimum sized 0.25μm transistors

VTC: Short Channel

V = 2 5

ID (mA)

0.25 0.375 0.25

p p

W L = 0.375 0.25

n n

W L =

VGS 2.5 V = 1 0 VGS = 1.25 VGS = 1.875

ID (mA)

0.20 0.15 0.10 0.05

PMOS

VGS = -1.875 VGS = -1.5 VGS = 1.0 VGS = 0.625 VGS = -0.625 VGS = -2.5

2.5
0.5
2.0
1.5
1.0

2.5 0.5 2.0 1.5 1.0

0.05
0.10

VDS (V)

VGS = -1.25

NMOS

VTC: Short Channel

0.25 0.20 VIN = 2.5

ID (mA)

0 25 VIN = 0.625 VIN = 0 0.10 VIN = 1.25 VIN = 1.875 V = 1 0 V = 1 0

VGS = 2.5 VGS = 1.0 VGS = 0.625 VGS = 1.25 VGS = 1.875 VGS = -0.625

ID (mA)

0.25 0.20 0.15 0.10 0.05

VGS = -1.25

Move the PMOS part to the first quadrant

VOUT (V)

2.5 0.5 2.0 1.5 1.0 VIN = 0.625 VIN = 1.875 VIN = 1.25 VIN = 1.0 VIN = 1.0

VGS = -1.875 VGS = -1.5 VGS = -2.5

2.5
0.5
2.0
1.5
1.0

2.5 0.5 2.0 1.5 1.0

0.05
0.10

VDS (V)

Vout (V)

2.5 2 0

VTC: Short Channel - Graphically

0.25 0.20 VIN = 2.5

ID (mA)

0.5 2.0 1.5 1.0

VTC

VIN = 0 0.10 VIN = 1.875

Vin (V)

2.5 0.5 2.0 1.5 1.0 VIN = 0.625

VOUT (V)

2.5 0.5 2.0 1.5 1.0 VIN = 0.625 VIN = 1.25 VIN = 1.875 VIN = 1.25 VIN = 1.0 VIN = 1.0

Switching Threshold: Short Channel

Vout (V)

2.5

The threshold VM is when VIN=VOUT

2.0 1.5 1.0

VM =1 V Vin (V)

2.5 0.5 2.0 1.5 1.0 0.5

SLIDE 11

11

Both NMOS and PMOS are velocity saturated

Switching Threshold: Short Channel

2 2

(( ) ) (( ) ) 2 2 Solving yields

DSATp DSATn n M Tn DSATn p DD M Tp DSATp M

V V k V V V k V V V V V − − = − + + 2 2 where 1

DSATp DSATn Tn DD Tp p DSATp M n DSATn

V V V r V V k V V r r k V ⎛ ⎞ + + + + ⎜ ⎟ ⎝ ⎠ = = + Minimum transistor dimensions

0.63; 1; 0.43; 0.4;

DSATn DSATp Tn Tp

V V V V = = − = = −

Example 0.25 μm technology

Parameters from the inside back

0.375 0.375 115 172.5; ( 30) 45 0.25 0.25 45 ( 1) 0.41 172.5 0.63

n p p DSATp n DSATn

k k k V r k V = × = = × − = − − × − = = = ×

the inside back cover in the book

0.63 1 0.43 0.41 2.5 0.4 2 2 2 2 1 1

DSATp DSATn Tn DD Tp M

V V V r V V V r ⎛ ⎞ ⎛ ⎞ + + + + + + − − ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ ⎝ ⎠ = = + 1.0 V 0.41 = +

IF VDD >> VDSAT and VT

⎛ ⎞

Example 0.25 μm technology

2 2 0.41 2.5 0.73 V 1 1 1 0.41

DSATp DSATn Tn DD Tp DD M

V V V r V V rV V r r ⎛ ⎞ + + + + ⎜ ⎟ × ⎝ ⎠ = ≈ = = + + +

V not high enough in this case VDD not high enough in this case

It is desirable to have VM around VDD/2

2 2

W V W V

Balancing the inverter

2 ' ' 2

(( ) ) (( ) ) 2 2 Assuming = yields

p DSATp n DSATn n M Tn DSATn p DD M Tp DSATp n p n p

W V W V k V V V k V V V V L L L L − − = − + +

2 ' 2 '

(( ) ) 2 (( ) ) 2

DSATn n M Tn DSATn p DSATp n p DD M Tp DSATp

V k V V V W V W k V V V V − − = − + +

SLIDE 12

12

Example using the same data

2 2

Balancing the inverter

2 2 ' 2 '

0.63 (( ) ) 115 ((1.25 0.43) 0.63 ) 2 2 3.5 1 30 ( 2.5 1.25 ( 0.4) ) (( ) ) 2 2

DSATn n M Tn DSATn p DSATp n p DD M Tp DSATp

V k V V V W V W k V V V V − − × − × − = = = − − × − + − − − − + − +

To be balanced, The PMOS should be 3.5 times wider than the NMOS times wider than the NMOS For the minimal NMOS with Wn=0.375 μm, the corresponding PMOS has Wp=1.3 μm

Balancing the inverter

1 5 1.6 1.7 1.8 0 8 0.9 1 1.1 1.2 1.3 1.4 1.5 M

V (V)

VM is rather insensitive to changes in the device ratio A ratio decrease from 3.5 to 2 yields VM = 1.13 V which often is acceptable Saves area

10 10

1

0.8

W p/W n

2

Determining VIH and VIL VIH and VIL when the slope is -1

1

OUT in

V V ∂ ⇒ = − ∂

1.5 2 2.5

Vout(V)

in

A reasonable approximation is to use the gain (g) around VM

0.5 1 1.5 2 2.5 0.5 1

Vin (V) V

OUT in

V g V Δ = Δ

Determining VIH and VIL A simplified piecewise linear VTC

Vout (V)

2.5

VIL

p

2.0 1.5 1.0

VM

OUT in

V g V Δ = Δ

Vin (V)

2.5 0.5 2.0 1.5 1.0 0.5

VIH

SLIDE 13

13 Determining VIH and VIL

DD M IL M

V V g V V − = −

Vout (V)

2.5

VIL

OUT in

V g V Δ = Δ

IL M DD M IL M

V V V V g V − = +

2.0 1.5 1.0

VM

IL

V -V VDD-VM M M IH M IH M

V g V V V V V g = − = −

Vin (V)

2.5 0.5 2.0 1.5 1.0 0.5

VIH VM-VIL

The Inverter Gain (g)

1 1 ( ) ( )( )

n DSATn p DSATp DSAT

k V k V r g V I V λ λ λ λ + + = − ≈ − −

Derived at page 189

( ) ( )( ) 2

DSATn D M n p M Tn n p

V I V V V λ λ λ λ − − −

8
6
4
2

Note that the gain is very sensitive to the

0.5 1 1.5 2 2.5

18
16
14
12
10

8

Vin (V) gain

y channel-length modulation Noise Margins

Vout (V)

2.5

VIL DD M IL M

V V V V g − = +

2.0 1.5 1.0

VM

IL

V -V VDD-VM

;

M IH M

g V V V g NM V V NM V = − = − =

Vin (V)

2.5 0.5 2.0 1.5 1.0 0.5

VIH VM-VIL

;

H DD IH L IL

NM V V NM V = = Example (Minimum sized transistors)

Vout (V)

2.5

VIL

1 ( )( ) 2

DSATn M Tn n p

r g V V V λ λ + ≈ − = − − −

2.0 1.5 1.0

VM

IL

V -V VDD-VM

( )( ) 2 1 0.41 0.63 (1 0.43 )(0.06 0.1) 2

M Tn n p

+ = − = − − +

Vin (V)

2.5 0.5 2.0 1.5 1.0 0.5

VIH VM-VIL

34.6 = −

SLIDE 14

14 Example (Minimum size transistors)

Vout (V)

2.5

VIL

2.5 1 1 0.96V 34.6

DD M IL M

V V V V g − − = + = + = −

2.0 1.5 1.0

VM

IL

V -V VDD-VM

1 1 1.03V 34.6 2.5 0.96 1.54V 1 03V

M IH M H DD IH

V V V g NM V V NM V = − = − = − = − = − = = =

Vin (V)

2.5 0.5 2.0 1.5 1.0 0.5

VIH VM-VIL

1.03V

L IL

NM V = =

Slightly to large values due to the approximation

CMOS Dynamic Behavior Capacitors Propagation delay Power consumption Inverter Load

CL Vin Vout Capacitance model for propagation d l l l ti

Cdb2 C 4 C d2

Vi V

t VDD

V

t2

delay calculations

Cdb1 Cdb2 Cg4 Cg3 Cw Cgd2

Vin Vout

Cgd1

Vout2

Inverter Load

Overlap Capacitance Junction Capacitance Wi C i

gd db

C C C = = Wire Capacitance Overlap & Gate Capacitance

w g

C C = =

VDD

Cdb1 Cdb2 Cg4 Cg3 Cw Cgd2

Vin Vout

Cgd1

Vout2

SLIDE 15

15 Cgd - Overlap Capacitance

Assumed to be in Cut-off or Saturation

No Channel Capacitance (at output side)

Only Overlap Capacitance

VDD

Only Overlap Capacitance

Cdb1 Cdb2 Cg4 Cg3 Cw Cgd2

Vin Vout

Cgd1

Vout2

The Miller Effect If Cgd is modeled from Vout to GND the value shall be doubled GND, the value shall be doubled

Cgd

V Δ ΔV

2C d

V Δ ΔV

2Cgd

Cgd = 2 Cgd0 W

Cdb - Junction Capacitance

db eq j

C K C = ×

VDD

Depends on grading coefficient Diode area and perimeter

Cdb1 Cdb2 Cg4 Cg3 Cw Cgd2

Vin Vout

Cgd1

Vout2

Cw - Wire Capacitance

Neglected on short distances I d i t i t h l i

VDD

Increased importance in new technologies

Cdb1 Cdb2 Cg4 Cg3 Cw Cgd2

Vin Vout

Cgd1

Vout2

SLIDE 16

16 Channel Capacitance

Region C g C gs C gd Cut off

C WL

Cut off

C OX WL eff

Linear

(1/2)C OX WL eff (1/2)C OX WL eff

Saturation

(2/3)C OX WL eff Cut off: No channel ⇒ CG = CGB Linear: Channel ⇒ Divide channel in two parts Saturation: ≈ 2/3 Channel connected to source

Cg - Gate Capacitance

Overlap – Cgs (Not Cgd) Ch l WLC

VDD

Channel – WLCox

Cdb1 Cdb2 Cg4 Cg3 Cw Cgd2

Vin Vout

Cgd1

Vout2

Inverter Load Model

Capacitor Expression C d 2C d0W

Vin Vout

CL

Model Cgd 2Cgd0W Cdb Keq(ACj+PCjsw) Cg Cgs0W+CoxWL Cw Area + Fringe Cap.

w

g p

The values differ for n- and p-channel The values differ for L to H / H to L Se table 5-2

Inverter - Transient Response

90

10

(1- ) ;

t

RC

ut

r

V e V t t t = =

10 10

t t − −

VDD

10

0.1 (1 ) 0.9 ln(0.9)

RC RC DD DD

V e V e t RC = − ⇔ = ⇔ = −

90

ln(0.1) ( l ( ) l ( )) t RC = −

CL Req-p

90 10

( ln(0.1) ln(0.9)) 2.2

r r

t t t RC t RC = − = − + = =

50

ln(0.5) 0.69

pHL pHL

t t RC t RC = = − = =

Req-n

SLIDE 17

17 Req in Short Channel Transistors

( ) ( /2) V V V V

R R +

( ) ( /2)

(

) ( /2)

2

OUT DD OUT DD

n V V n V V eq n DS DS D D V V V V

R R R V V I I

= = = =

+ = = ⎡ ⎤ ⎡ ⎤ + ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ ⎣ ⎦

( ) ( /2)

2

OUT DD OUT DD

D D V V V V eq n

R

= =

⎣ ⎦ ⎣ ⎦ =

Chapter 5

Digital IC-Design

The CMOS Inverter Cont.

Req in Short Channel Transistors

Graphical Method

0 15

(mA)

D

I 2 V V

In Velocity Saturation

0 5 0.1 0.15

2 V

GS

V =

/ 2

145 A

DVDD

I μ = 153 A

DVDD

I μ =

Saturation

(V)

DS

V 0.5 1 2

0.63 V

Req in Short Channel Transistors

/2

145 A; 153 A;

DVDD DVDD

I I μ μ = =

Graphical Method

/2 ( ) ( / 2)

OUT DD OUT DD

DVDD DVDD DS DS D D V V V V

V V I I R μ μ

= =

⎡ ⎤ ⎡ ⎤ + ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ ⎣ ⎦ = =

6

6

2

2 1 153 10 145 10 10 k 2

eq n eq n

R R

− −

+ × × = = Ω

SLIDE 18

18 Req in Short Channel Transistors

Model Based Method

1 3 5 2 1 2 (1 ) 4 6 (1 ) 2

DD DD DD eq DD DD DSAT DD DSAT DSAT

V V V R V V I V I I λ λ λ ⎛ ⎞ ⎜ ⎟ ⎛ ⎞ = + ≈ − ⎜ ⎟ ⎜ ⎟ + ⎝ ⎠ ⎜ ⎟ + ⎝ ⎠

2

with ( ) 2

DSAT

DSAT DD T DSAT

V I k V V V ⎛ ⎞ = − − ⎜ ⎟ ⎜ ⎟ ⎝ ⎠

In Velocity Saturation

Req for Short Channel NMOS Find IDSAT

0.1 0.15 (mA)

D

I 2 V

GS

V = ' 2 2

2 V; 0.43 V; 0.63 V; 115 mA/V 0.375 m; 0.25 m

DD T DSAT n

V V V k W V W μ μ = = = = = = ⎛ ⎞

(V)

DS

V 0.5 1 2

0.63 V

DSAT

I

IDSAT = ID when V = 0

' 2

( ) 2 0.375 0.63 115 (2 0.43)0.63 136 A 0.25 2

DSAT

DSAT n DD T DSAT DSAT

V W I k V V V L I μ ⎛ ⎞ = − − = ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ ⎛ ⎞ = − − = ⎜ ⎟ ⎝ ⎠

VDS = 0

(extrapolated)

Req in Short Channel Transistors

136 A; =0.06 V

DSAT

I μ λ = 1 3 5 2 1 2 (1 ) 4 6 (1 ) 2 2 1 2 3 2 5 2 1 0 06 2

DD DD DD eq DD DD DSAT DD DSAT DSAT

V V V R V V I V I I R λ λ λ ⎛ ⎞ ⎜ ⎟ ⎛ ⎞ = + ≈ − ⎜ ⎟ ⎜ ⎟ + ⎝ ⎠ ⎜ ⎟ + ⎝ ⎠ ⎛ ⎞ ⎜ ⎟ ⎛ ⎞ = + ≈ − × ⎜ ⎟ ⎜ ⎟

6 6 6

1 0.06 2 2 2 136 10 (1 0.06 2) 4 136 10 6 136 10 (1 0.06 ) 2 10.0 k 9

eq eq

R R

− − −

+ ≈ × ⎜ ⎟ ⎜ ⎟ × + × × ⎝ ⎠ ⎜ ⎟ × + × ⎝ ⎠ = Ω ≈ .9 k (1 % error) Ω

Inverter - Transient Response

VDD

3 15 3 15

2 ; 10 2.2 2.2 10 10 2 10 44 0 69 0 69 10 10 2 10 14

L eq n r

C fF R k t RC ps RC

− −

= = Ω = = × × × × =

CL Req-p

3 15

0.69 0.69 10 10 2 10 14

pHL

t RC ps

−

= = × × × × =

Req-n

SLIDE 19

19 Inverter - Propagation Delay

2 2

(

) / 2

/ 2 ( ) ( )

L OH OL L DD n n

Q C U C V V C V k k Q I t V V t V V t = ×Δ = =

Long Channel Transistors V

2 2 2

(

)

(

)

2 2 (

)

1 1 ( )

n n GS T pHL DD T pHL L DD L pHL n DD T n DD L

Q I t V V t V V t C V C t k V V k V C = × = × = × = ≈ CL 1 1 ( ) 2

L p DD n p

C t V k k = +

Ideal Vin (Step)

Propagation Delay (page 202) Short Channel Transistors V

3 0.69 4 0.52 ( ) 2

L DD pHL DSAT L DD DSATn n DSATn DD Tn

C V t I C V V k V V V = = = − −

Transistors

CL

Ideal Vin (Step)

Propagation Delay Simulation

5 x 10

11

Short Channel Transistors

pLH

t

pHL

t Fan-Out = 1

CL

V

3.5 4 4.5 tp(sec)

( )

p

t s

p

t

1 1.5 2 2.5 3 3.5 4 4.5 5 3

β

β = Wp/Wn

A ratio around 2 is close to optimum What Ratio Should be Chosen? Short-channel

Transistors Fan-Out = 1

p

W W β =

V

p

W

β=3.5 balance the inverter (VM=VDD/2) β=2 (or 2.4) for equal delays (tpLH=tpHL)

n

W

CL

n

W

However, β=2 might be acceptable (VM≈0.45 VDD)

SLIDE 20

20 Effect of Input Rise Time

tpHL Increase linearly with the

0 35

tpHL [ns]

Note the gain

input rise time trise

0.30 0.35 0.25 2 2 ( ) ( )

4

r pHL actual pHL step

t t t = +

gain

0.6 0.4 0.8 1.0

trise [ns]

0.2 0.20 0.15

Digital IC-Design

Driving a Large Fan-out

Inverter Chain

Out In

If CL is given:

How many stages are needed to minimize the delay?

CL

How many stages are needed to minimize the delay?

How to size the inverters?

Driving a Large Fan-Out

Typical examples: Busses

Driving a large capacitance

Clock network Control wires (e.g. set and reset signals) Memories (driving many storage cells)

VDD

Worst case: Off chip signals

CL

SLIDE 21

21 Inverter with Load (External only)

Delay Load (Cext)

Cext Req Req tp = 0.69 Req Cext

Internal (intrinsic) load is neglected Not the case in modern technologies

Inverter with Internal Load

Delay External Load

Cint Cext tp = 0.69 Req (Cint + Cext)

Self-loading if Cint dominate Should be avoided

3.6 3.8 x 10

11

Device Sizing (W scaled with S)

(for fixed load) External load

2.6 2.8 3 3.2 3.4 tp(sec)

Self-loading effect: Intrinsic capacitances dominate (W is to capacitances dominate

2 4 6 8 10 12 14 2 2.2 2.4 S

( wide compared to the load)

Driving Large Capacitances

Cint = Intrinsic capacitance Cext = Extrinsic capacitance Req Req = Resistance in channel

VDD

Cint = Cdb+Cgd Req

ext w g

C C C = +

Cw = Wire capacitance Cg = Gate C in next stage

Cint

DD

Cext Req Req

SLIDE 22

22 Scaling to Increase Driving Capability

Scaling W with a factor S:

Req Cint = Cdb+Cgd Req

int iref ref eq

C C R S R S = × =

VDD

Cint

DD

Cext Req Req

Scaling to increase driving capability

Delay RC-model

0.69 ( ) 0.69 (1 )

ext p eq int ext eq int

C t R C C R C = + = + 0.69 ( ) 0.69 (1 ) 0.69 (1 ) (1 )

p eq int ext eq int int ref ext ext p iref p iref iref

t R C C R C C R C C t S S C t C S S C + + = + = +

Scaling with a factor S tp0 = intrinsic delay Independent of S

Scaling Example (page 206)

19.3 ; 3.15 ; 3.0 1

p ext iref

t ps C fF C fF C = = = 1 (1 ) 19.3 (1 ) 1.05

ext p p iref

C t t S ps C S = + = + ×

C C Ciref Cext

Scaling Example (page 206)

1 19.3 (1 ) 1.05

p

p S t s = × + ×

30 40

tp (ps)

S =5, Substantial improvement S >10, ”No more gain”

S

5 10 15 10 20

SLIDE 23

23 Sizing a Chain of Inverters

int, j

C = C γ

γ = Capacitive proportionality

factor for each inverter

g,j

C

2 N 1

Technology Dependent
Independent of the size (W)
Close to 1 in Submicron

The in- and

utput

capacitive ratio Cg,N+1= CL Cg,1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N

Sizing a Chain of Inverters

, 1 , g j g j

C f = C

+ 2 N 1

f = The loading capacitive ratio in two following stages

Cg,N+1= CL Cg,1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N

Sizing a Chain of Inverters

int,j g,j

C = C γ

, 1 , g j g j

C f = C

+

, , 1 , , ,

(1 ) (1 ) (1 )

ext j g j j p j p p p int j g j

C C f t t t t C C γ γ

+

= + = + = +

2 N 1 Cg,N+1= CL Cg,1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N

Sizing a Chain of Inverters

,2 ,3 , , 1 ,2 , , , 1 , 1 g g g j L g j g g j g j g N g

C C C C f = C C C C C C

+ −

= = = = Total Delay:

Known

2 N 1

1

(1 )

N j p p j

f t t γ

=

= +

∑

Total Delay: If each stage is scaled with the same factor f

Cg,N+1= CL Cg,1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N

SLIDE 24

24 Sizing a Chain of Inverters

,2 ,1 g g

C f = C C

N L N

f = C C F = Known

2 N 1

,3 , ,1 2 1 g g N L g

C f = f = C C C F F = ( =overall effective fan-out)

,1 g

C Known

Cg,N+1= CL Cg,1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N

Sizing a Chain of Inverters

N

f F =

1

(1 ) (1 )

N N j p p p j

f F t t N t γ γ

=

= + = × + =

∑

(1 ) f

e f

γ +

=

Optimum is found by setting the derivative to 0

Cg,N+1= CL 2 N Cg,1 1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N

Sizing a Chain of Inverters

(1 ) f

e f

γ +

=

Has no closed form solution except for γ=0

f

so u o p

γ

γ=0 when intrinsic capacitance is neglected

f e =

Otherwise: f is solved numerically

Cg,N+1= CL 2 N Cg,1 1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N

6

Sizing a Chain of Inverters

Too many stages

p popt

t t Normalized delay

, 1 , g j g j

C f = C

+

6 4 Common Practice Around 4

f

2 1 2 5 4 3

1 (1 ) f

e f

+

= for

SLIDE 25

25 Buffer Design

1 64

N f tp 1 64 65

1 1 8 64 64 64 4 16

1 64 65 2 8 18 3 4 15

1 64 2.8 8 16 22.6

4 2.8 15.3

Inverter Chain Common practice:

O t I

1

Optimum fan-out around f=4

4 16

Out In CL

Digital IC-Design

Power Consumption

Dynamic Power Consumption

VDD

2 2

Energy charged in a capacitor

L DD

C V C V Charge

2

2 2 Energy is also discharged, i.e.

L DD C C tot L DD

C V C V E E E C V = = = Discharge

2

Power consumption

L DD

P f C V =

SLIDE 26

26

Note: The power is dissipated in the transistor

VDD

Dynamic Power Consumption

dissipated in the transistor resistance, Req However: the power consumption is independent

f the value of Req

Charge

f the value of Req

P = CL VDD

2 f

Discharge

Current Spikes – Direct Path

Current peak when both N- and PMOS are

2 2 2

peak r peak f r f dp DD DD DD peak

I t I t t t E V V V I × × × = + =

pen

2

r f dp DD peak

t t P V I f × =

VDD-VT VT

N open P open

Ipeak

Static Power Consumption Ileakage increases with decreasing VT

V

Pstat =Ileakage × VDD Drain leakage to bulk &

VDD

to bulk & drain-source subthreshold current Dynamic vs. Static Power

The dynamic and static power is about equal in the 65 nm Technology

ized power

1 0.01 100 65 nm

Dynamic power Normal

1990 2020 0.0000001 0.0001 2010 2000

Static power Year

Source: ITRS

SLIDE 27

27 Digital IC-Design

Power Delay Product (PDP) (PDP)

Power-Delay Product

Helps to measure the quality

f different circuit topologies

Energy per switching event For static CMOS

2 2 2

( ) 2 2

p L DD p L DD max p L DD p

t C V PDP P t C V f t C V J t × = × = × × × = × × =

Independent of operating frequency

Power-Delay Product

Energy per switching event

2 L DD

C V PDP P ×

If we lower the supply, the Energy and performance

2

L DD p

PDP P t = × =

2

C V ×

PDP will be reduced, but also the performance Some claims that EDP is a

2

L DD p p

C V EDP P t t × = × = ×

Some claims that EDP is a better measure since it includes the delay

Some Examples - Cascaded Inverters

Minimal Design Compensated to Decrease tpLH

Out VDD In Out

2 fF

10 kΩ

30 kΩ

10 kΩ 15 kΩ 10 ; 30 ; 4

eq n eq p Min

R k R k C fF

− −

= Ω = Ω =

GND

1 fF + 2 fF 3 fF 1 fF +

10 ; 15 ; 6

eq n eq Comp Comp

R k R k C fF

− −

= Ω = Ω =

SLIDE 28

28 Propagation Delay

10 ; 30 ; 15 ; 4 ; 6 ; 2

eq n eq p eq Comp Min Comp DD

R k R k R k C fF C fF V V

− − −

= Ω = Ω = Ω = = =

Not much faster but

0.69 28 0.69 83 0.69 41 0.69 62

pHL Min Min eq n pLH Min Min eq p pHL Comp Comp eq n pLH Comp Comp eq Comp

t C R ps t C R ps t C R ps t C R ps

− − − − − − − −

= × × = = × × = = × × = = × × =

VDD

55 52 2 2

pHL Min pLH Min p Min pHL Comp pLH Comp p Comp

t t t ps t t t ps

− − − − − −

+ = = + = =

more symmetric

Out VDD GND In Out In

Power Consumption at Max Speed

4 ; 6 ; 2 1 1 9 1 9 7

Min Comp DD

C fF C fF V V f GH f GH = = =

Compensating

2 2 2 2

9.1 ; 9.7 2 2 1 140 2 1 230 2

Max Min Max Comp p p Min Min DD Max Min L DD p Min Comp Comp DD Max Comp L DD p Comp

f GHz f GHz t t P C V f C V W t P C V f C V W t μ μ

− − − − − −

= = = = = × × = × × = = × × = × × =

VDD

gives higher power consumption

Out VDD GND In Out In

Power-Delay Product

2 2 2

( ) 2 2

p L DD p L DD max p L DD p

t C V PDP P t C V f t C V J t × = × = × × × = × × =

2 2

8 2 12 2

Min DD Min Comp DD Comp

C V PDP fJ C V PDP fJ × = = × = =

VDD

Compensating gives higher energy per switching event

Out VDD GND In Out In

Total Power Consumption and PDP

tot dyn dp stat

P P P P = + + =

2

r f L DD DD peak leakage DD

t t C V f V I f I V + = + +

2

( ) 2

L DD p