I I I -V CMOS: What have we learned from HEMTs ? J. A. del Alamo, - - PowerPoint PPT Presentation

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I I I -V CMOS: What have we learned from HEMTs ? J. A. del Alamo, - - PowerPoint PPT Presentation

Dec 26, 2022 152 likes •393 views

I I I -V CMOS: What have we learned from HEMTs ? J. A. del Alamo, D.-H. Kim 1 , T.-W. Kim, D. Jin, and D. A. Antoniadis Microsystems Technology Laboratories, MIT 1 presently with Teledyne Scientific 23rd International Conference on Indium

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SLIDE 1

1

I I I -V CMOS:

What have we learned from HEMTs?

  • J. A. del Alamo, D.-H. Kim1, T.-W. Kim, D. Jin, and D. A. Antoniadis

Microsystems Technology Laboratories, MIT

1presently with Teledyne Scientific

Acknowledgements:

  • Sponsors: Intel, FCRP-MSD
  • Labs at MIT: MTL, NSL, SEBL

23rd International Conference

  • n Indium Phosphide and Related Materials

Berlin, May 22-26, 2011

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SLIDE 2

2

Outline

  • Why III-Vs for CMOS?
  • What have we learned from III-V HEMTs
  • III-V CMOS device design and challenges
  • Conclusions
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SLIDE 3

CMOS scaling in the 21st century

  • Si CMOS has entered era of “power-constrained scaling”:

– Microprocessor power density saturated at ~100 W/cm2 – Microprocessor clock speed saturated at ~ 4 GHz

3

Intel microprocessors

Pop, Nano Res 2010

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SLIDE 4

Transistor scaling requires reduction in supply voltage Not possible with Si: performance degrades too much

Consequences of Power Constrained Scaling

Power = active power + stand-by power

PA~ f CVDD

2N N ↑  VDD ↓

4

#1 goal!

clock frequency transistor capacitance

  • perating voltage

transistor count

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SLIDE 5

5

How I I I -Vs allow further VDD reduction?

  • Goals of scaling:

– reduce transistor footprint – extract maximum ION for given IOFF

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SLIDE 6

6

How I I I -Vs allow further VDD reduction?

  • Goals of scaling:

– reduce transistor footprint – extract maximum ION for given IOFF

  • III-Vs:

– higher electron velocity than Si  ION ↑ – tight carrier confinement in quantum well  S ↓  VDD ↓

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SLIDE 7

S D

Etch stopper

Barrier Channel Buffer t ins

Oxide

t ch

Gate

Cap

7

What have we learned from I I I -V HEMTs?

7

  • QW channel (tch = 10 nm):
  • InAs core (tInAs = 5 nm)
  • InGaAs cladding
  • n,Hall = 13,200 cm2/V-sec
  • InAlAs barrier (tins = 4 nm)
  • Ti/Pt/Au Schottky gate
  • Lg=30 nm

Kim, EDL 2010

State-of-the-art: InAs HEMTs

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SLIDE 8

8

Lg= 30 nm I nAs HEMT

8

  • Large current drive: ION>0.5 mA/µm at VDD=0.5 V
  • VT = -0.15 V, RS=190 ohm.μm
  • High transconductance: gmpk= 1.9 mS/μm at VDD=0.5 V

8

Kim, EDL 2010

0.0 0.2 0.4 0.6 0.8 0.0 0.2 0.4 0.6 0.8

0.2 V 0.4 V 0 V

ID [mA/m] VDS [V]

VGS =

  • 0.6
  • 0.4
  • 0.2

0.0 0.2 0.0 0.5 1.0 1.5 2.0

gm [mS/m] VGS [V]

VDS = 0.5 V

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SLIDE 9

10

9

10

10

10

11

10

12

10 20 30 40

Frequency [Hz] Gains [dB]

  • 1

1 2 3

K

H21 K MSG/MAG Ug

Lg= 30 nm I nAs HEMT

9

  • Only transistor of any kind with both fT and fmax > 640 GHz
  • S = 74 mV/dec, DIBL = 80 mV/V, Ion/Ioff ~ 5x103
  • All FOMs at VDD=0.5 V

9

Kim, EDL 2010

  • 1.0
  • 0.8
  • 0.6
  • 0.4
  • 0.2

0.0 0.2 0.4 10

  • 9

10

  • 8

10

  • 7

10

  • 6

10

  • 5

10

  • 4

10

  • 3

VDS = 0.05 V VDS = 0.5 V

IG ID

VDS = 0.5 V

ID, IG [A/m] VGS [V]

VDS = 0.05 V

fT = 644 GHz fmax = 681 GHz

VDS=0.5 V, VGS=0.2 V

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SLIDE 10
  • FOM that integrates short-channel effects and transport:

ION @ IOFF=100 nA/µm, VDD=0.5 V InAs HEMTs: higher ION for same IOFF than Si: Why?

I nAs HEMTs: Benchmarking with Si

10 IEDM 2008

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SLIDE 11
  • 1. Very high electron injection velocity at the virtual source

EC vinj

  • vinj(InGaAs) increases with InAs fraction in channel
  • vinj(InGaAs) > 2vinj(Si) at less than half VDD
  • ~100% ballistic transport at Lg~30 nm

Why high I ON?

Kim, IEDM 2009 Liu, Springer 2010

11

EV

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SLIDE 12
  • 2. Quantum capacitance less of a bottleneck than previously

believed

InAs channel: tch = 10 nm

  • 0.4
  • 0.2

0.2 0.4 10 20 30 40 VG [V] Capacitance [fF/m2] Experiment (CG)

Cins ( tins = 4 nm) Ccent1 CQ1 (m||* = 0.026me ) CG (m||* = 0.026me ) CG ( 0.07 ) CG ( 0.05 )

Biaxial strain + non-parabolicity + strong quantization: m||

* ↑  CG ↑  ns ↑  ION ↑

Why high I ON?

Jin, IEDM 2009

12

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SLIDE 13
  • 3. Sharp subthreshold swing due to quantum-well channel
  • Dramatic improvement in short-channel effects with thin channel
  • Thin channel does not degrade vinj at Lg~40 nm (Kim, IPRM 2011)

Why high I ON?

Kim, IPRM 2010

13

60 70 80 90 160 40 200 120 80

InAs HEMTs: tch = 5 nm InAs HEMTs: tch = 10 nm In0.7Ga0.3As HEMTs: tch = 13 nm

Subtreshold swing [mV/dec]

Lg [nm]

tins = 4 nm, Lside = 80 nm

state-of-the-art Si

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SLIDE 14
  • 1.00
  • 0.75
  • 0.50
  • 0.25

0.00 0.25 0.50 10

  • 10

10

  • 9

10

  • 8

10

  • 7

10

  • 6

10

  • 5

10

  • 4

10

  • 3

VDS = 0.5 V

ID, IG [A/m] VGS [V]

tins = 10 nm tins = 7 nm tins = 4 nm

ID IG

14

Limit to I I I -V HEMT Scaling: Gate Leakage Current

tins ↓  IG↑  Further scaling requires high-K gate dielectric

14

InAs HEMT Lg = 30 nm tch = 10 nm

tins=4 nm tins=7 nm tins=10 nm

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SLIDE 15

15

I I I -V CMOS: device design and challenges

Intel’s 45 nm CMOS III-V HEMT

  • What do we preserve?
  • What do we change?

~2 m

Modern III-V HEMT vs. modern Si MOSFET:

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SLIDE 16

I I I -V CMOS: HEMT features worth preserving

16

  • Quantum-well channel: key to scalability
  • Undoped channel:
  • InAs-rich channel:

for high mobility and velocity

  • Buried-channel design:
  • Raised source and drain regions: essential for scalability
  • Undoped QW channel in extrinsic regions: key to low access resistance
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SLIDE 17

I I I -V CMOS: HEMT features to change

17

  • Schottky gate: need MOS gate with very thin high-K dielectric
  • T-gate: need rectangular gate
  • Barrier under contacts: need to eliminate
  • Alloyed ohmic contacts: change to refractory ohmic contacts
  • Source and drain contacts: need self-aligned with gate
  • Footprint: need to reduce by 1000 X!

n+ n+

QW-MOSFET HEMT

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SLIDE 18

I I I -V CMOS:

  • ther critical needs

18

  • p-channel MOSFET: with performance >1/3 that of n-MOSFET
  • Co-integration of n-FET and p-FET on Si: compact, planar surface

n-MOSFET p-MOSFET Silicon

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SLIDE 19

I I I -V CMOS:

  • ther designs

19

n+ n+

Regrown S/D QW-MOSFET FinFET Gate-all-around nanowire FET Etched S/D QW-MOSFET

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SLIDE 20

20

The high-water mark: I ntel’s I nGaAs Quantum-Well MOSFET

  • Direct MBE on Si substrate (1.5 m buffer thickness)
  • InGaAs buried-channel MOSFET (under 2 nm InP barrier)
  • 4 nm TaSiOx gate dielectric by ALD, Lg=75 nm
  • First III-V QW-MOSFET with better performance than Si

Radosavljevic, IEDM 2009

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SLIDE 21

More recent notable work

Al2O3/InGaSb QW- MOSFET (Stanford) Nainani, IEDM 2010

p+ InP Fin-Channel Fin-Channel

Drain Source

p InP

EXT.

Gate

Fin-channel p+ InP Fin-Channel Fin-Channel Fin-Channel Fin-Channel

Drain Source

p InP

EXT.

Gate

Fin-channel

InGaAs FinFET (Purdue, Intel) Wu, IEDM 2009 Radosavljevic, IEDM 2010 InAs Nanoribbon MOSFETs

  • n Insulator (UC Berkeley)

Ko, Nature 2010

Si SiO2 InAs G S D

XOI InAs MOSFET

Aspect Ratio Trapping (Amberwave) Fiorenza, ECS 2010

21

Self-aligned QW-FET (MIT) Kim, IEDM 2010 Ge p-type QW-MOSFET (Intel) Pillarisetty, IEDM 2010

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SLIDE 22

22

Conclusions

  • III-V HEMTs suggest strong potential for III-V CMOS:

– InAs electron injection velocity > 2x that of Si at 1/2x VDD – Quantum capacitance less of a bottleneck than previously believed – Quantum-well channel yields outstanding short-channel effects

  • Impressive recent progress on III-V CMOS

– Sub-100 nm InGaAs MOSFETs with ION > than Si at 0.5 V demonstrated

  • Lots of work ahead

– Demonstrate ~10 nm III-V N-MOSFET that is better than Si – P-channel MOSFET – N-channel + P-channel cointegration on Si