Modeling Frequency Response of 65 nm CMOS RF Power Devices CMOS RF - - PowerPoint PPT Presentation

Modeling Frequency Response of 65 nm CMOS RF P D i CMOS RF Power Devices

U h G i i1 J d l Al

1

Usha Gogineni1, Jesus del Alamo1, Christopher Putnam2, David Greenberg3

1Massachusetts Institute of Technology, Cambridge, MA 2IBM Microelectronics, Essex Jct, VT, 3IBM Watson Research, NY

Email: ushag@mit.edu

Sponsorship: SRC, Intel Fellowship

Theme /Task: 1661. 002

Outline

• Motivation
• Measured Data on 65 nm CMOS

– fT, fmax as a function of device width

• Small-signal Equivalent Circuit Extraction
• Analytical Model for f and f
• Analytical Model for fT and fmax
• Conclusions

Conclusions

Usha Gogineni / 1

Motivation

• Great interest in using CMOS for mm-wave power applications
• However, Pout < 20 mW at 18 GHz [1]
• Output power does not scale with width in wide devices

65nm CMOS

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• 1. J. Scholvin, IEDM 2006

Motivation

• Why doesn’t output power scale in wide devices?
• High frequency power performance correlates with fmax

Key Questions:  How does fmax scale in wide devices?  Can we predict f f for a given device layout?  Can we predict fT, fmax for a given device layout?

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Technology and Layout Details

Gate

• 65 nm CMOS from IBM

G t L th 50

Gate

S D

Sx S

D S

• Gate Length = 50 nm
• Gate Width = 96 m to 1536 m

G Sx Sx

• Unit Cell: 24 fingers of 2 m width
• W ↑ by parallelizing multiple unit cells

Gate

Unit cell: W = 48 m

• S-parameters from 0.5 GHz to 40 GHz
• Open and short de-embedding

Gate Drain Source

p g

Gate Drain Source

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4 Unit cells: W = 192 m

Measured Data - fT, fmax

fT ↓ and fmax ↓ as W ↑

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Small-signal Equivalent Circuit

To understand fT, fmax width scaling: construct small-signal equivalent circuit

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Small-signal Parameter Extraction

Measure S-parameters @ VGS=VDS=0 V Convert to Y-parameters

21 )

Re( Y g m 

1. 3.

) Re(

12 11

Z Z R G  

@

GS DS

Convert to Z-parameters

22 21

) Re( 1 ) ( Y r g

• m

 ) Re( ) Re(

12 22 12

Z Z R Z R

D S

  

2 12 22 12 22

)) (Im( ) Re( Y Y Y Y R sx   

Measure S-parameters @ VDS=1 V, ID=100 mA/mm

 ) Im( ) Im(

12 12 11

Y Y Y C gs  

2.

Convert to Z-parameters Subtract RG, RS, RD

 ) Im( ) Im(

12 22 12

Y Y C C Y C

b db gd

    

 Intrinsic Z-parameters Cgb by fitting in ADS

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 C C

sb db

Ref: D. Lovelace, Microwave Symposium, 1994

Measured vs Modeled s-parameters

W = 96 m VDD = 1 V I 100 A/ ID = 100 mA/mm

Modeled Measured

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Model fits measured s-parameters well

Measured vs Modeled fT, fmax

W = 96 m VDD = 1 V I = 100 mA/mm ID = 100 mA/mm

Model fits measured h21 and U at all frequencies

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Width Dependence of Intrinsic Parameters

VDD = 1V VDD 1V ID = 100 mA/mm

= 1/ro

Intrinsic parameters scale ideally with W

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Width Dependence of Parasitic Resistances

VDD = 1V I = 100 mA/mm ID = 100 mA/mm

Source Gate Drain Source 2 cells 8 cells 32 cells

RS constant, RG ↑ and RD ↑ as W ↑

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fT, fmax sensitivity

fT, fmax sensitivity to 100% change in small-signal parameters:

‐50 ‐40 ‐30

fmax (%)

‐20 ‐10

n fT and f

10 10

Change in

10 20

C

Scale ideally Minor Impact

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RG, RD have big impact on fmax and do not scale well Scale ideally Minor Impact

Reason for fmax degradation

Does poor scalability of RG, RD alone explain fmax degradation? Use small-signal model for W = 96 m device in ADS Use small signal model for W 96 m device in ADS RG ↑ 120% and RD ↑ 180% keeping all else constant fT fmax Modeled

W 96 R R ↑ 142 GHz → 112 GHz 180 GHz → 95 GHz W: 96 m. RG, RD ↑

Measured

W: 96 m -1536 m 142 GHz → 110 GHz 190 GHz → 90 GHz W: 96 m 1536 m

W ↑  fT ↓ because RD ↑

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W ↑  fmax ↓ because RG and RD ↑

Analytical Expressions for fT, fmax

• Useful to have simple expressions for fT and fmax
• Substrate parameters (Rsx, Cdb, Csb, Cgb) ignored
• 2 and higher order terms ignored
• Traditional derivations for fmax only include RG

    1

m T

R R g f

Tasker’s [2] expression:

            )) 1 )( ( 1 ( ) 1 ( 2

• m

S D gd

• S

D gs

r g R R C r R R C 

) ( 1 R R g R g g   

New expression:

) 2 ( ( )) 2 2 ( ) ( ) )( (( ) 1 ( ) ( [ 4 ) ( 1

2 2 2 max ds m G gd gs D S D G S G ds m ds m D G gd S m ds S G gs S D ds S m m

g g R C C R R R R R R g g g g R R C R g g R R C R R g R g g f                

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)] ) 2 3 5 (

2 S G m D S D G S G ds m

R R g R R R R R R g g    

• 2. Tasker, EDL ‘89

Measured and Analytical fT, fmax

• Excellent agreement between analytical and measured data

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g y

• Model useful to understand impact of width scaling on high frequency

characteristics

Conclusions

• Studied frequency response of 65 nm CMOS devices
• fT and fmax decrease with increasing device width
• Accurate small signal circuit parameters extracted
• Accurate small-signal circuit parameters extracted
• fT, fmax ↓ because RG and RD ↑ as W ↑
• Analytical model of fT, fmax models width behavior well

Key to enabling CMOS for mm-wave applications is a iti h h d i i id d i

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parasitic-aware approach when designing wide devices

Technology Transfer

Liaison Interactions:

• Industrial Liaisons: David Greenberg, Alberto Valdes Garcia

(IBM Microelectronics) (IBM Microelectronics)

• Several teleconferences with liaisons over academic year
• More frequent interaction during internships

q g p

• Device designs done with input from Liaisons

Internships:

• Summer 2007 and summer 2008 at IBM Microelectronics
• Design work carried out at IBM Microelectronics
• 65 nm and 45 nm designs manufactured by IBM
• 65 nm and 45 nm designs manufactured by IBM

Publications / Presentations:

Task reports published on SRC website regularly

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Task reports published on SRC website regularly SiRF 2010: 45 nm power and frequency response