A Novel DPS Integrator for Fast CMOS Imagers J. M. Margarit, J. - - PowerPoint PPT Presentation

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A Novel DPS Integrator for Fast CMOS Imagers J. M. Margarit, J. - - PowerPoint PPT Presentation

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ISCAS08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 1/17 A Novel DPS Integrator for Fast CMOS Imagers J. M. Margarit, J. Sabadell, L. Ters and F. Serra-Graells System Integration

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SLIDE 1

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 1/17

A Novel DPS Integrator for Fast CMOS Imagers

  • J. M. Margarit, J. Sabadell, L. Terés and F. Serra-Graells

System Integration Department Institut de Microelectrònica de Barcelona Centro Nacional de Microelectrónica - CSIC Spain

May 2008

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 2

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 2/17

1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 3

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 3/17

1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 4

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 4/17

In-pixel ADC

◮ Architecture?

X Direct (flash) X Algorithmic (success. approx.) Predictive (Σ∆)

◮ Feedback = relaxed analog specs ◮ Pulse modulator + digital filter

PWM ≡ time-to-first spike PDM ≡ spike counting No external clocks Switching power ∝ signal X Signal loss due to reset times

+

  • DAC

Pulsedensitymodulator Digital filter Isens Vpulse qadc Vpulse qadc Vint +

  • Vth

binit FPA Isens

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 5

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 5/17

1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 6

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 6/17

PDM for Fast Imaging

◮ Classic topology: ◮ CTIA to cancel

input parasitics

◮ Correlated double

sampling (CDS) for noise cancellation

◮ Ideally:

Vint Cint CCDS Cpar Vpulse binit+Vpulse

binit+Vpulse

Vref V V

ref th

+ Isens

qadc = ⌊nadcideal⌋ nadcideal = Tframe Tpulseideal = Tframe CintVth Isens

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 7

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 7/17

Real Scenario

◮ Loss due to

reset time: nadcreal = Tframe Tpulseideal + Tres nadcreal = nadcideal 1 +

Tres Tframe nadcideal

◮ Non-linearity error:

nerror = |nadcreal−nadcideal|

◮ Maximum at full-scale:

max(nerror) = qfullscale −

qfullscale 1+

Tres Tframe qfullscale < 0.5LSB = 1

2

Tres <

Tframe 2q2

fullscale

for qfullscale ≫ 1 e.g. qfullscale = 1023(10bit) Tframe = 10ms ⇒ Tres < 5ns

Vint Vpulse Vref binit Vint Vpulse Tframe

Tpulseideal Tpulsereal Tres

V V

ref th

+ Vref V V

ref th

+

1 2 3 4 5 6 7 1 2 3 4 5 6

Not compatible with low-power nor low-voltage!

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 8

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 8/17

1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 9

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 9/17

Reset-Insensitive Topology

◮ Charge controlled reset

  • f the PDM integrator

◮ Continuous-time

integration (like APS!)

◮ Built-in CDS mechanism ◮ Switch charge injection

similar to classic topology

Vint Cint Vref Creset/CDS Vpulse binit

Vpulse

Cpar Isens V V

ref th

+

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 10

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 10/17

Real Scenario

◮ During reset, charge

from Isens and Creset/CDS is combined and integrated in Cint.

◮ Almost ideal, even for

Tpulsereal ∼ Tres.

◮ Minimum Tres required

for redistribution. . .

◮ . . . but Tres value not

relevant (technology independence).

Vint Vpulse binit Vint Vpulse Tframe

Tpulseideal Tpulsereal Tres

Vref V V

ref th

+ Vref V V

ref th

+

1 2 3 4 5 6 7 1 2 3 4 5 6 7

True low-power and low-voltage compatible!

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 11

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 11/17

1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 12

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 12/17

CMOS Proposal

◮ 3-stage compact

PDM circuit

◮ Single transistor

CTIA stage M1

◮ Local reference M2 ◮ Built-in threshold

comparator M3 (all in weak inversion): Vth = nUt ln (W /L)1 (W /L)3

Cpar Vint Cint Vref Isens Creset/CDS

M1 M2 M3

Ibias Ibias Ibias Vpulse binit

Vpulse Vpulse

◮ Technology mismatching

Cint ↔ Creset/CDS, M1↔M2 and M1↔M3 are equivalent to ∆Vth

◮ ∆Vth reduction through DPS area increase

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 13

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 13/17

1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 14

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 14/17

Quasi-Static (QS) Stimulus

1000 800 600 400 200 Digitaloutput[LSB] 1 2 3 4 5 1 0.5 0.2 0.1 1 0.5 0.2 0.1 1 2 3 4 5

ClassicPDM ProposedPDM

◮ 0.18µm 1-poly 6-metal

CMOS technology

◮ Design parameters:

Cint,reset/CDS=100fF, Vref =1V, (W /L)1=20(W /L)3 so Vth=0.1V and Tframe=2ms

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 15

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 15/17

Non Quasi-Static (NQS) Stimulus

1000 800 600 400 200 1 2 3 4 5 1 2 3 4 5

ClassicPDM ProposedPDM

Digitaloutput[LSB] time Tframe

◮ Non systematic loss

even at low amplitudes for classic PDM

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 16

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 16/17

1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica

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SLIDE 17

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 17/17

Conclusions

◮ Novel pulse density modulator (PDM) for high-speed DPS. ◮ Reset-insensitive analog integrator proposal. ◮ Low non-linearity for low-power and low-voltage operation. ◮ Compact CMOS circuit realization. ◮ Comparative study in 0.18µm 1-poly 6-metal technology. ◮ Robust simulation results for both QS and NQS signals.

  • J. M. Margarit et al.

Centro Nacional de Microelectrónica