A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS - - PowerPoint PPT Presentation

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A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS - - PowerPoint PPT Presentation

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ISCAS07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 1/19 A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS Imagers F. Serra-Graells, J. M. Margarit and L. Ters System Integration Department

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SLIDE 1

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 1/19

A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS Imagers

  • F. Serra-Graells, J. M. Margarit and L. Terés

System Integration Department Institut de Microelectrònica de Barcelona Centro Nacional de Microelectrónica - CSIC Spain

May 2007

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 2

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 2/19

1 Introduction 2 Pixel Architecture Proposal 3 Low-Power CMOS Building Blocks 4 Experimental Results 5 Conclusions

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 3

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 3/19

1 Introduction 2 Pixel Architecture Proposal 3 Low-Power CMOS Building Blocks 4 Experimental Results 5 Conclusions

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 4

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 4/19

Scenario

ADC I/O digital image map sensorFPA hybrid pad (bumping, postprocess...) digital gain map CMOSread-out array digitalpixelsensor(DPS)

Active pixel requirements

◮ Hybrid imager ⇒

high input cap

◮ Room temp. IR ⇒

large dark current

◮ FPA signal integrity ⇒

digital only I/O

◮ FPN compensation ⇒

individual pixel gain programmability

◮ Large FPA ⇒

low-power & compact pixel circuits

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 5

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 5/19

1 Introduction 2 Pixel Architecture Proposal 3 Low-Power CMOS Building Blocks 4 Experimental Results 5 Conclusions

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 6

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 6/19

Digital pixel sensor (DPS) proposal

Isens

  • ffset

cancel.

Idark Cint

DAC digital integrator + I/O

Vth

DPS cell

Vcom

analog integrator

Cpar

individualgaincontrol digitalread-out

Cpar

comp. localbias

Vint Ieff

digitalprogramming-in

bin bout Vspike

ADC

◮ Automatic input dark

current & capacitance compensation

◮ Asynchronous ADC

based on spike counting

◮ Individual gain control:

FPN compensation Spatial AGC Updated each frame No speed reduction

◮ Built-in analog

references

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 7

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 7/19

1 Introduction 2 Pixel Architecture Proposal 3 Low-Power CMOS Building Blocks 4 Experimental Results 5 Conclusions

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 8

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 8/19

Input offset and capacitance compensation

Isens Vcom Cpar M1 M2 M3 M4 M5 Ibias Ieff Idark M6 M7 M8

cal

Ibias Cdark

◮ Low impedance input:

rin = 1 gmg5

  • 1

n +

gmg1,2 gmd1,2+gmd3,4

  • ≪ 1kΩ

so, Cpar can be >10pF. . .

◮ Regulated cascode

dark current copier: Mismatch insensitive Large dark-to-signal ratio ∼ 1µA 1nA

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 9

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 9/19

Integrating ADC

Ieff M9 Cint Ibias M10 Ibias Vint Vth Vspike Ibias Vspike Vspike M11 M12 M13 M14 M15 M16 M17 M18 M19

◮ Fast reset times can be obtained. Ideally:

fspike = 1 CintVth Ieff

◮ 3-switch reset

CTIA stage: More parasitic insensible Constant input voltage CDS implementation Low-power Class-AB

◮ Dynamic bias

comparator

◮ Cint linearity

not needed

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 10

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 10/19

Digital integrator and I/O

Q Q D init init D clk Q Q qin qout eout ein count

M20 Vspike

clk init qout qin clk init qout qin clk bin init clk bout init eout ein eout ein count count

1...N

count

◮ Circuit reuse:

Ripple counter Shift register

◮ Modular design ◮ Overflow detector ◮ In case of no overflow:

wout = fspike fframe = Tframe CintVth Ieff

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 11

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 11/19

Self-biasing

Vref Ibias M24 M21 M22 M23 M26 P 1 M25 (M21-M22 in weak inv. + M25 in strong inv.)

Vref = Ut ln(P) Ibias ≃ β W L

  • 25

(VDD − VTO) Vref

◮ Local I/V reference:

Low crosstalk Compact circuit

◮ Low process sensitivity ◮ Bias mismatching between DPS cells:

σ ∆Vref Vref

  • =

1

  • (WL)21,22

AVTO nVref

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 12

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 12/19

FPN compensation

Csamp Vth

DPS

Cmem gaincodesequence imagecodesequence

clk clk edac

shift register mode

edac bi

Vint Vspike

count bin bout

◮ Offset cancellation already

addressed by the input copier

◮ Built-in DAC for gain

correction: Vth = VDD

N

  • i=1

bN−i 2i No speed reduction Individual for each DPS Changeable each frame

◮ Suitable for spatial AGC

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 13

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 13/19

1 Introduction 2 Pixel Architecture Proposal 3 Low-Power CMOS Building Blocks 4 Experimental Results 5 Conclusions

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 14

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 14/19

CMOS integration (first version)

pad vdda vdda gnda gnda gndd gndd vddd vddd gndd gndd vddd vddd gndd gndd 10 m ¹

100µm×100µm

◮ Room temperature

PbSe IR sensor target

◮ Design parameters:

Cint 500 fF N 10 bit P 12 Ibias 50 nA Cmem,samp 100 fF

◮ 0.35µm 2-polySi 4-metal

CMOS technology

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 15

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 15/19

CMOS integration (first version)

PTAT cal cal 10 m ¹ Analogintegrator andADC Digitalintegrator andI/O DAC edac edac clk clk ninit ninit count count qout qin M6 ( ) Cdark Cint Cmem Csamp

100µm×100µm

◮ Room temperature

PbSe IR sensor target

◮ Design parameters:

Cint 500 fF N 10 bit P 12 Ibias 50 nA Cmem,samp 100 fF

◮ 0.35µm 2-polySi 4-metal

CMOS technology

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 16

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 16/19

Results (first version)

◮ Test vehicle:

3×10 pixel FPA NMOS sensor emulator

◮ Performance:

Dark current range 0.1-5 µA Dark current retention time 2-10 s

  • Max. input capacitance

15 pF Signal range 1-1000 nA Integration time 1 ms Crosstalk <0.5 LSB Programming/read-out speed 10 Mbps Supply voltage 3.3 V Static power consumption <1 µW Biasing deviations (±σ) ±15 % Total Silicon area 100×100 µm2

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 17

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 17/19

Last minute results (second version)

◮ Shared DAC for programming Vth & Idark at alternating frames:

digital Idark control for Vth=’1000000000’ Digitalread-out[LSB] Isens [nA]

'1111111111' '0000000000' '0100000000' '1100000000' '1000000000'

digital Vth control for Idark=’1000000000’ Digitalread-out[LSB] Isens [nA]

'1000000000' '0100000000' '1100000000' '1010000000' '0110000000'

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 18

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 18/19

1 Introduction 2 Pixel Architecture Proposal 3 Low-Power CMOS Building Blocks 4 Experimental Results 5 Conclusions

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona

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SLIDE 19

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 19/19

Conclusions

◮ Novel low-power and digital-only I/O DPS cell ◮ Hybrid imager compatibility ◮ Pixel built-in FPN compensation and biasing generation ◮ Circuit implementation for all building blocks ◮ 0.35µm 2-polySi 4-metal CMOS demonstrator

  • F. Serra-Graells, J. M. Margarit and L. Terés

Institut de Microelectrònica de Barcelona