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IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 1/19 A Self-Biased PLL-Tuned AER Pixel for High-Speed Infrared Imagers J.M. Margarit, M. Dei , L. Ters and F. Serra-Graells josepmaria.margarit@imb-cnm.csic.es Integrated

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SLIDE 1

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 1/19

A Self-Biased PLL-Tuned AER Pixel for High-Speed Infrared Imagers

J.M. Margarit, M. Dei , L. Terés and F. Serra-Graells

josepmaria.margarit@imb-cnm.csic.es Integrated Circuits and Systems (ICAS) Instituto de Microelectrónica de Barcelona, IMB-CNM(CSIC)

May 2011

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 2

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 2/19

1 DPS Introduction 2 Log-Domain Temporal Contrast 3 Reset-Insensitive High-Speed AER 4 PLL-Based Tuning 5 CMOS Design Example 6 Conclusions

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 3

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 3/19

1 DPS Introduction 2 Log-Domain Temporal Contrast 3 Reset-Insensitive High-Speed AER 4 PLL-Based Tuning 5 CMOS Design Example 6 Conclusions

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 4

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 4/19

DPS Introduction

◮ Uncooled MWIR PbSe

VPD technology

◮ High-speed (>1Kfps)

vision for automotive, process control. . . ◮ Compact and low-power CMOS circuits ◮ High dark-to-signal current ratios ◮ Tunable temporal contrast to match applications ◮ High-speed spiking insensitive to AER delay

Vcom CMOS read-out circuit Digital pixel sensor (DPS) PbSe sensor Isens MWIR Arbitrer Encoder Event address Focal plane array Isens Vcom Vint Iint Ibias Non-stop reset Window comparator pos neg reset AER interface req ack

  • utn
  • utp

Analog integrator Temporal contrast

tune

ftune High-speed spike generation PLL Itune Digital tuning

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 5

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 5/19

1 DPS Introduction 2 Log-Domain Temporal Contrast 3 Reset-Insensitive High-Speed AER 4 PLL-Based Tuning 5 CMOS Design Example 6 Conclusions

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 6

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 6/19

Log-Domain Temporal Contrast

◮ Dark current cancellation ◮ Emphasis on high-freq. contents ◮ Self-biasing capability

◮ I-domain low-pass linear ODE

dIbias dt = 2πfc (Isens − Ibias)

◮ Subthreshold companding (M1-M2)

ID = 2nβU 2

t IS

e

VGB−VTO nUt

e

− VSB

Ut

◮ V -domain non-linear ODE (M3-M4)

Cbias dVbias dt

  • Icap

= 2πfcnUtCbias

  • Itune
  • e

Vsens−Vbias nUt

− 1

  • Vcom

M2 M5 M3 M4 M1

Itune Vtune Cint Vbias Vsens Isens Iint Isens Ibias Ibias

M6 M7

N 1 1 N N Vint Cbias Icap J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 7

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 7/19

Log-Domain Temporal Contrast

◮ Dark current cancellation ◮ Emphasis on high-freq. contents ◮ Self-biasing capability

◮ I-domain low-pass linear ODE

dIbias dt = 2πfc (Isens − Ibias)

◮ Subthreshold companding (M1-M2)

ID = 2nβU 2

t IS

e

VGB−VTO nUt

e

− VSB

Ut

◮ V -domain non-linear ODE (M3-M4)

Cbias dVbias dt

  • Icap

= 2πfcnUtCbias

  • Itune
  • e

Vsens−Vbias nUt

− 1

  • ◮

Corner frequency tuning

Frequency [Hz]

1m 10m 100m 1 10 10 1K 10K 100K 1M 10M

  • 20
  • 40
  • 60
  • 80
  • 100
  • 120
  • 140
  • 160
  • 180

Gain [dB] Itune=1nA 100p 100f 10f 1f 1p 10p

◭ Itune programmability?

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 8

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 8/19

1 DPS Introduction 2 Log-Domain Temporal Contrast 3 Reset-Insensitive High-Speed AER 4 PLL-Based Tuning 5 CMOS Design Example 6 Conclusions

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 9

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 9/19

Reset-Insensitive High-Speed AER

◮ CTIA-based integration for

high-speed imaging (Cint ↓) ◭ Spiking frequency non-linearity at high-rate due to AER delay: f ′

req =

freq 1 + tresfreq freq = |Iint| CintVth

Iint Vint Cint

reset

(a) Vref

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 10

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 10/19

Reset-Insensitive High-Speed AER

◮ CTIA-based integration for

high-speed imaging (Cint ↓) ◭ Spiking frequency non-linearity at high-rate due to AER delay: f ′

req =

freq 1 + tresfreq freq = |Iint| CintVth ◮ Novel reset-insensitive schemes based on charge injection:

  • Inherent CDS?
  • Extra capacitors?
  • Low-impedance sources?

Iint Vint Cint

reset

(a) Iint Vint Cint Cres Vref

reset

(b) Iint Vint Cint Cres Vref

reset

(d) Iint Vint Cint Cres Vref

reset

(c) Vref +Vth

reset

Vref

Dead Voltage Cap time CDS sources area (a) × ×

  • (b)
  • ×

×× × (c)

  • ×

× (d)

  • ×

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 11

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 11/19

Reset-Insensitive High-Speed AER

◮ CTIA-based integration for

high-speed imaging (Cint ↓) ◭ Spiking frequency non-linearity at high-rate due to AER delay: f ′

req =

freq 1 + tresfreq freq = |Iint| CintVth ◮ Novel reset-insensitive schemes based on charge injection with inherent CDS ◮ Compact and low-power CMOS circuit realization Vth = ±nUtM ln (P)

M1

Cint Iint Vint Ibias MCint

neg

M2

Ibias

M4 M5 1/P

pos

M3

Ibias

M6 M7

ackd

P 1

pos neg pos pos ack ack ack ack req pos neg neg neg ackd ackd ackd

M8

  • utp

pos ack

  • utn

neg ack

pos pos ack

  • utp

Time tarb

req

tack tres

init init

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 12

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 12/19

1 DPS Introduction 2 Log-Domain Temporal Contrast 3 Reset-Insensitive High-Speed AER 4 PLL-Based Tuning 5 CMOS Design Example 6 Conclusions

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 13

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 13/19

PLL-Based Tuning

◮ Temporal contrast fc

◭ Weak integrity pA-range Itune

◮ Digital frequency tuning based

  • n in-pixel PLL:

ftune = Itune 2VthvcoCvco Vthvco = nUt ln

  • 1 + Y

1 + 1/X

  • ◮

Robust KHz-range clocking ◮ Process and thermal compensation for Itune ◮ Dynamic and adaptive contrast?

M4

Itune

M1 M3

1 X Vvco

M5 M8 M7 slow fast

Charge pump

M2

1

vco

Vctrl PFD

M6

VCO

tune2 tune1 tune1 tune1

1 Y

tune2 tune1

Vvco

vco slow fast

Time Vthvco Cvco

fc = 1 π Cvco Cbias ln

  • 1 + Y

1 + 1/X

  • ftune

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 14

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 14/19

1 DPS Introduction 2 Log-Domain Temporal Contrast 3 Reset-Insensitive High-Speed AER 4 PLL-Based Tuning 5 CMOS Design Example 6 Conclusions

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 15

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 15/19

CMOS Design Example

◮ 0.35µm 2P4M CMOS technology ◮ Design parameters: Idark≃1µA,

N=4, Cint=80fF, M=3/2, P=4, X=1, Y =2 and Cvco/Cbias=15 ◮ 40µm-pitch DPS

  • utn
  • utp
  • utn
  • utp

vdd req ack tune1 tune2 init gnd vdd req ack tune1 tune2 init gnd

10 m ¹ PbSe pad

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 16

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 16/19

CMOS Design Example

◮ 0.35µm 2P4M CMOS technology ◮ Design parameters: Idark≃1µA,

N=4, Cint=80fF, M=3/2, P=4, X=1, Y =2 and Cvco/Cbias=15 ◮ 40µm-pitch DPS ◮ Good 0.12MHz/nA linearity up to the spiking rate hard limit

1 tarb+tack ≃27MHz

freq [Hz]

100p 10M 1M 100K 10K 1n 10n 100n

Iint [A]

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 17

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 17/19

CMOS Design Example

◮ 0.35µm 2P4M CMOS technology ◮ Design parameters: Idark≃1µA,

N=4, Cint=80fF, M=3/2, P=4, X=1, Y =2 and Cvco/Cbias=15 ◮ 40µm-pitch DPS ◮ Good 0.12MHz/nA linearity up to the spiking rate hard limit

1 tarb+tack ≃27MHz

◮ Process and temperature compensation for the temporal contrast fc ◮ Power consumption ∝ 2Idark

fc [Hz]

10 100 1K 10K 100K 1M 10M 10 100 1K 10K 100K 1M 10M

ftune [Hz]

typical mean, 27ºC worse speed, 27ºC typical mean, 60ºC J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 18

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 18/19

1 DPS Introduction 2 Log-Domain Temporal Contrast 3 Reset-Insensitive High-Speed AER 4 PLL-Based Tuning 5 CMOS Design Example 6 Conclusions

J.M. Margarit et al. IMB-CNM(CSIC)

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SLIDE 19

IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 19/19

Conclusions

◮ Novel DPS circuit for uncooled MWIR PbSe sensors ◮ Log-domain filtering for temporal contrast and self-biasing ◮ AER insensitive spike generation with inherent CDS ◮ Digital PLL-based temporal contrast tuning with process

and thermal compensation

◮ A 40µm-pitch DPS design example in 0.35µm 2P4M CMOS

technology ◮ Currently, a 128×128 imager is under development in 0.15µm 1P6M CMOS technology. . . Thanks for your attention!

J.M. Margarit et al. IMB-CNM(CSIC)