Low power, small die-size PLL using semi-digital storage instead of - - PowerPoint PPT Presentation

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Low power, small die-size PLL using semi-digital storage instead

• f big loop filter capacitance

Presented by: Markus Dietl

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Outline

• Conventional PLL design approach / Proposed PLL design architecture
• Circuit description of major blocks
• Mathematical modeling of the PLL loop in Z-domain
• Simulation results / LAB measurements
• Scope for further development (future work)

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Problem statement/ Introduction

• To design a low bandwidth PLL (Bandwidth ~1-2KHz)
• Very low power(< 500uA)
• Low rms Jitter,C2C Jitter & period Jitter
• Low die-size (aggressive pricing)
• No External component

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Traditional PLL concepts (Propotional Damping/Storage)

) ( ) ( ) ( n V n V n V

stored prop control

+ =

!

=

" # =

n i i stored

C t Icp n V ) (

) ( ) ( n V K n f

control

! =

R Icp

Traditional:

C +

update i prop

T t R Icp n V ! " " = ) (

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Proposed PLL (at nth update)

!

=

" # =

n i i stored

C t Icp n V ) (

R Icp C +

update n prop

T t R Icp n V ! " " = ) (

Replaced by Semi-digital storage (M storage cells) Analog Damping used with ripple cap

) ( ) ( ) ( n V K n V K n f

prop prop M j j step

! + ! ="

=

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PLL during locking

Held digitally low

2R Icp1 Cstoragecell_1

update i prop

T t R Icp n V ! " " =

1

) (

Icp2_1

2R Cstoragecell_M

Icp2_n

OSC_ring

Cstoragecell_x

Icp2_x

Cstoragecell_x+1

Icp2_x+1

Storagecell X & X+1 activ

!

=

" # = > <

n activ i i

C t Icp n x V

_ 2

) (

) ( 1 = > < n V

VDD n M V = > < ) (

!

=

" # = > + <

n activ i i

C t Icp n x V

_ 2

) ( 1

Two active cells For Analog tuning

Held digitally high

Analog Damping

) ( )) ( ( ) ( n V K n V VDD K n f

prop prop M j j step

! + " ! =#

=

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Ripple cap N Storage cells Proposed PLL block Diagram

PVT compensation With digital/semi-digital information VCO tuning with 2 analog & N-2 digital bits REFCUR

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Voltage controlled Oscillator

Wide VCO Range Propotional Analog damping

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Storage Cells & control

N Semi-digital storage cells PVT compensated Charge pump

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APLL/DPLL/Proposed Semi-digital PLL

Characteristic Analog PLL Digital PLL Proposed PLL Bandwidth(with

• nchip compon-

ents only) 10K-1/10th of Reference freq. <1Hz-1MHz <1Hz -1/10th of Reference freq. Quantization noise NO Yes NO Simplicity Yes NO Yes Noise CP/LPF/Resistane noise gets amplified with high VCO gain Quantization noise due to low VCO gain, CP/ Resistance noise amplification is negligible

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VCO gain from semi-digital storage (spice simulation): VCO acts linear (no freq. step)

20 VCO steps, from 30 to 50 VCO behaves like having N*vdd tuning voltage with very low gain

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PLL_1

___ ______________________________________ _____________________ _____________________ _______________________ dt[s] prop relative outpu tperio d change feed back devider VCO gain [Hz/step]

Ip 15 10

6 !

" := N 2344 := ft 77 106 # := Kp 78 106 " := dt 70 10

6 !

# := Ko 0.4 10

6

" :=

___ ______________________________________ _____________________ _____________________ _______________________ Tper -> Tphase in:

R 16 103 # := C 1.2 10

9 !

# := fup ft N := FB

VC O

Ko ft2 := Z s ( ) e

s fup

:= f2p s ( ) 1 1 1 Z s ( ) ! := AB s ( ) f2p s ( ) Ip fup # Kp 1 ft2 # 1 R s C # + # 1 Z s ( ) # FB

VC O

dt 1 Z s ( ) 1 ! # +

$ % % % % & ' ( ( ( ( )

# := HZ s ( ) N AB s ( ) 1 N AB s ( ) + := G

Z s

( ) N AB s ( ) := EZ s ( ) 1 1 N AB s ( ) + := _____________________________________________________________________________________ x 1 1.02 , 8 .. := f x ( ) 10x := s f x , ( ) 2 * # f x ( ) # i # :=

10 100 1 103 " 1 104 " 1 105 " 10 ! 8 ! 6 ! 4 ! 2 ! 2 4

MAGNITUDE

20 log EZ s f x , ( ) ( )

( )

# 20 log HZ s f x , ( ) ( )

( )

# f x ( )

Z-Modeling of the PLL

2 2

Icp C

vdd l storagecel

dt

!

=

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PLL_1ws

C 1.2 10 9

!

" :=

___ ___________________________________________ ___________________________________________ _____ ____________ dt[s] prop relative outpu tperio d change VCO gain [Hz/step]

Ipw 14.6 10 6

!

# := Kow 0.4 106 # := Kpw 58 106 # := Rw 18 103 " := dtw 84 10 6

!

" := Ips 15.8 10 6

!

# := dts 64 10 6

!

" := Kos 0.52 106 # := Kps 98 106 # := Rs 14 103 " :=

_____________________________________________________________________________________ x 1 1.02 , 8 .. := f x ( ) 10x := s f x , ( ) 2 ! " f x ( ) " i " :=

10 100 1 103 # 1 104 # 1 105 # 10 $ 8 $ 6 $ 4 $ 2 $ 2 4

MAGNITUDE

20 log EZs s f x , ( ) ( )

( )

" 20 log HZs s f x , ( ) ( )

( )

" 20 log EZw s f x , ( ) ( )

( )

" 20 log HZw s f x , ( ) ( )

( )

" f x ( )

Z-Modeling of PLL– Weak & Strong

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PLL CLOSED LOOP spice simulation nom

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Closed loop Bandwidth Simulations (spice ) 0dB @ 200Hz

• 1.25dB @ 1KHz
• 3dB @ 2KHz
• 6.5dB @ 3KHz

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Phase noise plot (lab measurement)

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Lab Measurement: C2C & period Jitter

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Conclusion

• Proposed is a new PLL architecture for low bandwidth applications
• No External capacitor is needed here.
• Power consumption of the device is very low
• Ripple capacitor is reduced by 1/15th and performance is equivalent to

the device with PLL having an external capacitance and bigger die size.

• Scope for further work

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Scope for further work

• We will explore this architecture for High bandwidth PLL’s
• We have plan to check this architecture for bandwidth <1Hz; for Jitter

cleaner applications

• There is a scope for further chip size reduction by sharing the capacitor

used in storage cells for active & inactive cells

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Thanks for joining the presentation

Markus Dietl / Puneet Sareen TI-Germany Phone: ++49/8161/80 3237 ++49/8161/80 3540 E-Mail: m-dietl1@ti.com p-sareen@ti.com

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Backup slides

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Z domain Model of a conventional PLL

PLL is a Loop that will create a Period, and compare the resulting edge at t_sys with the edge of the Reference Clock at t_ref.

PFD N CP/ LF

• K

f 2 1/z(s) T ref T sys t_ref t_sys Delta_t Control Voltage T sys * N

+

1/z(s)

+

Z(s):= exp(-s Tref)

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Capacitance: Current to Voltage

!

=

" # =

n i i

t Icp n Q ) (

i

t Icp i Q ! " = ) (

PFD produces each update a pulse with the width !ti . During this time the charge pump current is flowing. So a charge will be deposited, with the size of:

The capacitance translates that into : After n updates the total deposited charge is:

!

=

" # =

n i i stored

C t Icp n U ) (

1/z(s)

+

IP2

1/C

!ti

Ustored

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Resistance: Current to Voltage

Icp R T t i U

update i prop

! ! " = ) (

Icp R i V ! = ) (

PFD produces each update a pulse with the width !ti . During this time the charge pump current is flowing and produces a voltage drop over the damping resistor, with the size of:

The rest of the update period no voltage drop is produced, so the average voltage drop is:

Icp R/Tupdate

!ti

Ustored

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Z domain Model of a voltage / word controlled PLL

z N s z dt f step K s z p ref T R f prop K z N s z dt f step K s z p ref T R f prop K

I I Z Feedback Z Forward Z Forward

Z H Z H

1 1 ) ( 1 2 _ ) ( 1 1 1 2 _ 1 1 ) ( 1 2 _ ) ( 1 1 1 2 _

) ( 1 ) ( ) ( ) ( 1 ) (

) ( ) (

! " ! ! " !

" + " " + " + " " +

= =

PFD N IP

K_step f 2 . dt

1/z(s) T ref T sys t_ ref t_sys Delta_t Control Voltages T sys * N

+

1/z(s)

+

Z(s):= exp(-s Tref)

• 1/z(s)

+

R/Tref 1/z(s) CHARGE

+ K_prop f 2

V/DCO

Stored Period

2 2

Icp C

vdd l storagecel

dt

!

=