Frequency Synthesizers for RF Transceivers Modelling of PLL in the - - PowerPoint PPT Presentation

CP-PLL models Design Example

Dottorato di Ricerca in Ingegneria Elettronica Informatica e delle Telecomunicazioni

Frequency Synthesizers for RF Transceivers

Modelling of PLL in the frequency and time domain with a design example

• E. Franchi, A. Gnudi, M. Guermandi

ARCES - University of Bologna

July, 20th 2010 - Short Course on RF electronics for wireless communication and remote sensing systems

CP-PLL models Design Example

Outline

1 CP-PLL models The need for accurate PLL models s-domain model z-domain model Time-domain model Comparison between models Phase Noise Models 2 Design Example: Frequency Synthesizer for UWB MB-OFDM UWB communications Synthesizer Architecture PLLs Tuning Range Extension Measured results

CP-PLL models Design Example

Outline

1 CP-PLL models The need for accurate PLL models s-domain model z-domain model Time-domain model Comparison between models Phase Noise Models 2 Design Example: Frequency Synthesizer for UWB MB-OFDM UWB communications Synthesizer Architecture PLLs Tuning Range Extension Measured results

CP-PLL models Design Example

Charge Pump Phase Locked Loops (CP-PLLs)

LOOP VCO DIVIDER FREQ REF

UP

F

DN REF DIV

F F

OUT

DETECTOR FILTER FREQ PHASE PUMP CHARGE

Charge Pump Phase Locked Loop PFD-CP compares phase misalignment between feedback and reference signal. Loop Filter integrates error signal and controls VCO output frequency. When in-lock FOUT = N · FREF . Loop tracks phase and frequency misalignments with zero errors.

CP-PLL models Design Example

Charge Pump Phase Locked Loops (CP-PLLs)

LOOP VCO DIVIDER FREQ REF

UP

F

DN REF DIV

F F

OUT

DETECTOR FILTER FREQ PHASE PUMP CHARGE

Charge Pump Phase Locked Loop CP , LF and VCO are continuous-time systems. PFD and FD are edge-driven systems. Phase comparison is performed once per reference period, not continuously.

CP-PLL models Design Example

The need for accurate PLL models

PLL models Simulations need to be performed hierarchically. Circuit level time-domain simulation is not feasible.

CP-PLL models Design Example

The need for accurate PLL models

PLL models Simulations need to be performed hierarchically. Circuit level time-domain simulation is not feasible. Traditional models (s-domain and z-domain) rely on linearizations and approximations to simplify loop analysis.

CP-PLL models Design Example

The need for accurate PLL models

PLL models Simulations need to be performed hierarchically. Circuit level time-domain simulation is not feasible. Traditional models (s-domain and z-domain) rely on linearizations and approximations to simplify loop analysis. Efficient semi-analytical time-domain models can avoid these approximations, with reduced computation time.

CP-PLL models Design Example

The need for accurate PLL models

PLL models Simulations need to be performed hierarchically. Circuit level time-domain simulation is not feasible. Traditional models (s-domain and z-domain) rely on linearizations and approximations to simplify loop analysis. Efficient semi-analytical time-domain models can avoid these approximations, with reduced computation time. Derivation and comparison between these models is performed.

CP-PLL models Design Example

Outline

1 CP-PLL models The need for accurate PLL models s-domain model z-domain model Time-domain model Comparison between models Phase Noise Models 2 Design Example: Frequency Synthesizer for UWB MB-OFDM UWB communications Synthesizer Architecture PLLs Tuning Range Extension Measured results

CP-PLL models Design Example

Fourth order PLL s-domain model

Approximation Charge injected by charge pump over one period: Q = θr−θd

2π GT

θ θ θ

VCO

K

VCO LPF

C

1 N FD s

2π r d

V G (s)

• G

LF

CP

PFD

2 1 π

REF DIV Icp t t t QC ∆θ −2π π π π π −3π 3 2 −

CP-PLL models Design Example

Fourth order PLL s-domain model

Approximation Charge injected by charge pump over one period: Q = θr−θd

2π GT

If the loop dynamic is slow enough one can neglect the CP current actual shape

θ θ θ

VCO

K

VCO LPF

C

1 N FD s

2π r d

V G (s)

• G

LF

CP

PFD

2 1 π

REF DIV Icp t t t QC ∆θ −2π π π π π −3π 3 2 −

CP-PLL models Design Example

Fourth order PLL s-domain model

Approximation Charge injected by charge pump over one period: Q = θr−θd

2π GT

If the loop dynamic is slow enough one can neglect the CP current actual shape and substitute it with an average current: iCP = G θr−θd

2π

θ θ θ

VCO

K

VCO LPF

C

1 N FD s

2π r d

V G (s)

• G

LF

CP

PFD

2 1 π

REF DIV Icp t t t QC ∆θ −2π π π π π −3π 3 2 −

CP-PLL models Design Example

Fourth order PLL s-domain model

Approximation Charge injected by charge pump over one period: Q = θr−θd

2π GT

If the loop dynamic is slow enough one can neglect the CP current actual shape and substitute it with an average current: iCP = G θr−θd

2π

Averaged linear continuous time PLL model

θ θ θ

VCO

K

VCO LPF

C

1 N FD s

2π r d

V G (s)

• G

LF

CP

PFD

2 1 π

REF DIV Icp t t t QC ∆θ −2π π π π π −3π 3 2 −

CP-PLL models Design Example

s-domain model transfer functions

CP-PFD

iCP = G θr−θd

2π

→

ICP(s) θr(s)−θd(s) = G 2π

θ θ θ

VCO

K

VCO LPF

C

1 N FD s

2π r d

V G (s)

• G

LF

CP

PFD

2 1 π

REF DIV Icp t t t QC ∆θ −2π π π π π −3π 3 2 −

CP-PLL models Design Example

s-domain model transfer functions

CP-PFD

iCP = G θr−θd

2π

→

ICP(s) θr(s)−θd(s) = G 2π 3rd order LF

GLF(s) = VC(s)

ICP(s) =

KLF

s+1/τz s·(s+b/τz)·(s+c/τz)

θ θ θ

VCO

K

VCO LPF

C

1 N FD s

2π r d

V G (s)

• G

LF

CP

PFD

2 1 π

CP-PLL models Design Example

s-domain model transfer functions

CP-PFD

iCP = G θr−θd

2π

→

ICP(s) θr(s)−θd(s) = G 2π 3rd order LF

GLF(s) = VC(s)

ICP(s) =

KLF

s+1/τz s·(s+b/τz)·(s+c/τz) QVCO

fo = KVCO · VC, θo =

• 2πfo(t)dt

→ θo(s)

VC(s) = 2π·KVCO s

θ θ θ

VCO

K

VCO LPF

C

1 N FD s

2π r d

V G (s)

• G

LF

CP

PFD

2 1 π

CP-PLL models Design Example

s-domain model transfer functions

CP-PFD

iCP = G θr−θd

2π

→

ICP(s) θr(s)−θd(s) = G 2π 3rd order LF

GLF(s) = VC(s)

ICP(s) =

KLF

s+1/τz s·(s+b/τz)·(s+c/τz) QVCO

fo = KVCO · VC, θo =

• 2πfo(t)dt

→ θo(s)

VC(s) = 2π·KVCO s FD θd(s) θo(s) = 1 N

θ θ θ

VCO

K

VCO LPF

C

1 N FD s

2π r d

V G (s)

• G

LF

CP

PFD

2 1 π

CP-PLL models Design Example

Fourth order PLL s-domain model

θ θ θ

VCO

K

VCO LPF

C

1 N FD s

2π r d

V G (s)

• G

LF

CP

PFD

2 1 π

Open loop transfer function... Gc(s) = G · KVCO · GLF (s) s · N

CP-PLL models Design Example

Fourth order PLL s-domain model

θ θ θ

VCO

K

VCO LPF

C

1 N FD s

2π r d

V G (s)

• G

LF

CP

PFD

2 1 π

Open loop transfer function... Gc(s) = G · KVCO · GLF (s) s · N ... for third order LF ... Gc(s) = KC s + 1/τz s2 · (s + b/τz) · (s + c/τz)

CP-PLL models Design Example

Fourth order PLL s-domain model

θ θ θ

VCO

K

VCO LPF

C

1 N FD s

2π r d

V G (s)

• G

LF

CP

PFD

2 1 π

Open loop transfer function... Gc(s) = G · KVCO · GLF (s) s · N ... for third order LF ... Gc(s) = KC s + 1/τz s2 · (s + b/τz) · (s + c/τz) ... with KC = GKVCOKLF N .

CP-PLL models Design Example

Fourth order PLL s-domain model

θ θ θ

VCO

K

VCO LPF

C

1 N FD s

2π r d

V G (s)

• G

LF

CP

PFD

2 1 π

Open loop transfer function... Gc(s) = G · KVCO · GLF (s) s · N Closed loop transfer function θo θr = G · KVCON · GLF (s) s · N + G · KVCO · GLF (s) ... for third order LF ... Gc(s) = KC s + 1/τz s2 · (s + b/τz) · (s + c/τz) ... with KC = GKVCOKLF N .

CP-PLL models Design Example

Fourth order PLL s-domain model

θ θ θ

VCO

K

VCO LPF

C

1 N FD s

2π r d

V G (s)

• G

LF

CP

PFD

2 1 π

Open loop transfer function... Gc(s) = G · KVCO · GLF (s) s · N Closed loop transfer function θo θr = G · KVCON · GLF (s) s · N + G · KVCO · GLF (s) ... for third order LF ... Gc(s) = KC s + 1/τz s2 · (s + b/τz) · (s + c/τz) ... with KC = GKVCOKLF N .

N log f cfz bfz

Gc 1+Gc Gc

log f fz fc π

arg( ) 20log(| |) m

φ

CP-PLL models Design Example

Fourth order PLL s-domain model

θ θ θ

VCO

K

VCO LPF

C

1 N FD s

2π r d

V G (s)

• G

LF

CP

PFD

2 1 π

Open loop transfer function... Gc(s) = G · KVCO · GLF (s) s · N Closed loop transfer function θo θr = G · KVCON · GLF (s) s · N + G · KVCO · GLF (s) ... for third order LF ... Gc(s) = KC s + 1/τz s2 · (s + b/τz) · (s + c/τz) Rule of thumb for design fc = 1 tlockζe(φm) ln fstep ferror

• N

log f cfz bfz

Gc 1+Gc Gc

log f fz fc π

arg( ) 20log(| |) m

φ

CP-PLL models Design Example

Outline

1 CP-PLL models The need for accurate PLL models s-domain model z-domain model Time-domain model Comparison between models Phase Noise Models 2 Design Example: Frequency Synthesizer for UWB MB-OFDM UWB communications Synthesizer Architecture PLLs Tuning Range Extension Measured results

CP-PLL models Design Example

Fourth order PLL z-domain model

PFD granularity effects when the loop bandwidth is too large. Compute z-domain model by

1

Substitute to the real CP input, weighted impulses of same area as the real pulse.

2

Compute open loop impulse response gc(t) antitransforming GC(s).

3

Sample the obtained equation every T.

4

Z-transform to obtain GD(z).

5

Compute closed-loop transfer function from GD(z).

CP-PLL models Design Example

Z-domain model

Antitransform open loop transfer function GC(s) = KC

• As + B

s2 + C s +

b τz

+ D s +

c τz

CP-PLL models Design Example

Z-domain model

Antitransform open loop transfer function GC(s) = KC

• As + B

s2 + C s +

b τz

+ D s +

c τz

• Impulse response

gc(t) = KC[Au(t) + Bt + Ce

− bt τz + De − ct τz ]

CP-PLL models Design Example

Z-domain model

Antitransform open loop transfer function GC(s) = KC

• As + B

s2 + C s +

b τz

+ D s +

c τz

• Impulse response

gc(t) = KC[Au(t) + Bt + Ce

− bt τz + De − ct τz ]

Sampled impulse response gd(n) = KC[Au(nT)+BnT +Ce

− bnT τz +De − cnT τz ]

CP-PLL models Design Example

Z-domain model

Antitransform open loop transfer function GC(s) = KC

• As + B

s2 + C s +

b τz

+ D s +

c τz

• Impulse response

gc(t) = KC[Au(t) + Bt + Ce

− bt τz + De − ct τz ]

Sampled impulse response gd(n) = KC[Au(nT)+BnT +Ce

− bnT τz +De − cnT τz ]

z-Transform GD(z) =   KCTAz z − 1 + KCBT 2z (z − 1)2 + KCTCz z − e

− bT τz

+ KCTDz z − e

− cT τz

 

CP-PLL models Design Example

Z-domain model - Step five

Closed loop transfer function TD(z) = θo(z) θi(z) = N · GD(z) 1 + GD(z)

CP-PLL models Design Example

Z-domain model - Step five

Closed loop transfer function TD(z) = θo(z) θi(z) = N · GD(z) 1 + GD(z) Antitransforming θo(n) =

4

• i=1

hu(i) · θo(n − i) +

3

• i=1

hv(i) · θi(n − i)

CP-PLL models Design Example

Z-domain model - Step five

Closed loop transfer function TD(z) = θo(z) θi(z) = N · GD(z) 1 + GD(z) Antitransforming θo(n) =

4

• i=1

hu(i) · θo(n − i) +

3

• i=1

hv(i) · θi(n − i) With hu(1) = β + γ + 2 + A′(β + γ + 1) − B′T+ +C′(γ + 2) + D′(β + 2) hu(2) = −1 − 2β − 2γ − βγ+ −A′(γβ + γ + β) + B′T(β + γ)+ −C′ · (2γ + 1) − D′(2β + 1) hu(3) = 2βγ + β + γ + A′βγ+ −B′Tγβ + C′γ + D′β hu(4) = βγ hv(1) = −A′(β + γ + 1) + B′T+ −C′(γ + 2) − D′(β + 2) hv(2) = A′(γβ + γ + β) − B′T(β + γ)+ +C′ · (2γ + 1) + D′(2β + 1) hv(3) = −A′γ + B′Tγβ − C′γ − D′β

CP-PLL models Design Example

Outline

1 CP-PLL models The need for accurate PLL models s-domain model z-domain model Time-domain model Comparison between models Phase Noise Models 2 Design Example: Frequency Synthesizer for UWB MB-OFDM UWB communications Synthesizer Architecture PLLs Tuning Range Extension Measured results

CP-PLL models Design Example

Limits of s- and z-domain models

s-domain model Relies on the fact that PFD input signal misalignment is sampled so fast that it can be considered a continuous-time operation. Might fail for wideband PLLs.

CP-PLL models Design Example

Limits of s- and z-domain models

s-domain model Relies on the fact that PFD input signal misalignment is sampled so fast that it can be considered a continuous-time operation. Might fail for wideband PLLs. z-domain model Assumes PFD input signal misalignment is small (pulses ≈ impulses). Might fail for large frequency jumps.

CP-PLL models Design Example

CP-PLL time-domain model

Classical time-domain simulation limits We need to simulate at least for the settling time (several Tref) while resolving time-steps of fractions of the VCO period. Too many simulation steps to resolve output frequency with desired precision. Tens-of-hours required.

CP-PLL models Design Example

CP-PLL time-domain model

Classical time-domain simulation limits We need to simulate at least for the settling time (several Tref) while resolving time-steps of fractions of the VCO period. Too many simulation steps to resolve output frequency with desired precision. Tens-of-hours required. Better solution Solve state equation describing loop behavior analytically. Compute system state variables only on few points per period.

CP-PLL models Design Example

CP-PLL time-domain model

Better solution Solve state equation describing loop behavior analytically. Compute system state variables only on few points per period.

ref div Vc t p

inf

t t sup q

CP-PLL models Design Example

CP-PLL time-domain model

Next DIV transition found inverting tsup

tinf

fout(t)dt = N

τ q = T − (i−1) p = − (i−1) t = 0

inf

τ ref div τ τ q = T − (i−1) + (i) t = 0

inf

τ p = − (i−1) ref div τ q = T + (i) p = (i−1) τ τ

sup

t = T + (i) ref div τ τ (i) τ t = T + q(i) = T τ (i−1) (i)

sup

p(i) = > 0, > 0 ref div t =

inf

τ τ τ < 0, < 0 (i−1) (i)

sup

τ τ τ τ τ τ < 0, > 0

sup

(i−1) (i) t = T − (i−1) + (i) (i−1) (i−1) t = (i) t = T − (i−1) + (i)

inf

τ(i−1) > 0, < 0 τ τ t

inf

t p t sup q t Vc t

sup

t q

inf

t p Vc p Vc q t sup t inf p t Vc t

inf

t sup q

CP-PLL models Design Example

CP-PLL time-domain model

Next DIV transition found inverting tsup

tinf

fout(t)dt = N Substituting tsup

tinf

• KVCO · vc(t) + f0
• dt = N

τ q = T − (i−1) p = − (i−1) t = 0

inf

τ ref div τ τ q = T − (i−1) + (i) t = 0

inf

τ p = − (i−1) ref div τ q = T + (i) p = (i−1) τ τ

sup

t = T + (i) ref div τ τ (i) τ t = T + q(i) = T τ (i−1) (i)

sup

p(i) = > 0, > 0 ref div t =

inf

τ τ τ < 0, < 0 (i−1) (i)

sup

τ τ τ τ τ τ < 0, > 0

sup

(i−1) (i) t = T − (i−1) + (i) (i−1) (i−1) t = (i) t = T − (i−1) + (i)

inf

τ(i−1) > 0, < 0 τ τ t

inf

t p t sup q t Vc t

sup

t q

inf

t p Vc p Vc q t sup t inf p t Vc t

inf

t sup q

CP-PLL models Design Example

CP-PLL time-domain model

Next DIV transition found inverting tsup

tinf

fout(t)dt = N Substituting tsup

tinf

• KVCO · vc(t) + f0
• dt = N

Integrating time-independent terms tsup

tinf

vc(t)dt = N − f0(tsup − tinf ) KVCO .

τ q = T − (i−1) p = − (i−1) t = 0

inf

τ ref div τ τ q = T − (i−1) + (i) t = 0

inf

τ p = − (i−1) ref div τ q = T + (i) p = (i−1) τ τ

sup

t = T + (i) ref div τ τ (i) τ t = T + q(i) = T τ (i−1) (i)

sup

p(i) = > 0, > 0 ref div t =

inf

τ τ τ < 0, < 0 (i−1) (i)

sup

τ τ τ τ τ τ < 0, > 0

sup

(i−1) (i) t = T − (i−1) + (i) (i−1) (i−1) t = (i) t = T − (i−1) + (i)

inf

τ(i−1) > 0, < 0 τ τ t

inf

t p t sup q t Vc t

sup

t q

inf

t p Vc p Vc q t sup t inf p t Vc t

inf

t sup q

CP-PLL models Design Example

CP-PLL time-domain model

Next DIV transition found inverting tsup

tinf

fout(t)dt = N Substituting tsup

tinf

• KVCO · vc(t) + f0
• dt = N

Integrating time-independent terms tsup

tinf

vc(t)dt = N − f0(tsup − tinf ) KVCO .

τ q = T − (i−1) p = − (i−1) t = 0

inf

τ ref div τ τ q = T − (i−1) + (i) t = 0

inf

τ p = − (i−1) ref div τ q = T + (i) p = (i−1) τ τ

sup

t = T + (i) ref div τ τ (i) τ t = T + q(i) = T τ (i−1) (i)

sup

p(i) = > 0, > 0 ref div t =

inf

τ τ τ < 0, < 0 (i−1) (i)

sup

τ τ τ τ τ τ < 0, > 0

sup

(i−1) (i) t = T − (i−1) + (i) (i−1) (i−1) t = (i) t = T − (i−1) + (i)

inf

τ(i−1) > 0, < 0 τ τ t

inf

t p t sup q t Vc t

sup

t q

inf

t p Vc p Vc q t sup t inf p t Vc t

inf

t sup q

Time-domain solver We analitically integrate the term on the left (depending on the 4 cases) and, every Tref we numerically invert the obtained equation.

CP-PLL models Design Example

Outline

1 CP-PLL models The need for accurate PLL models s-domain model z-domain model Time-domain model Comparison between models Phase Noise Models 2 Design Example: Frequency Synthesizer for UWB MB-OFDM UWB communications Synthesizer Architecture PLLs Tuning Range Extension Measured results

CP-PLL models Design Example

Estimated settling time for variable fref/fc

s-domain vs. time-domain

10 20 30 fref / fc 5 10 Settling time error (%) 4

th order

3

rd order

2

nd order

fz = 0.25fc, τ0 = Tref (wide frequency jump) Unreliable for fref /fc < 10 (it also fails to predict instability).

CP-PLL models Design Example

Estimated settling time for variable fref/fc

s-domain vs. time-domain z-domain vs. time-domain

10 20 30 fref / fc 5 10 Settling time error (%) 4

th order

3

rd order

2

nd order

fz = 0.25fc, τ0 = Tref (wide frequency jump) Unreliable for fref /fc < 10 (it also fails to predict instability).

10 20 30 fref / fc 5 10 15 20 25 Settling time error (%) 4

th order

3

rd order

2

nd order

fz = 0.25fc, τ0 = Tref (wide frequency jump) Error can be higher than for s-domain model due to large τ0 but predicts instability.

CP-PLL models Design Example

Estimated settling time for variable fref/fc

s-domain vs. time-domain z-domain vs. time-domain

10 20 30 fref / fc 5 10 Settling time error (%) 4

th order

3

rd order

2

nd order

10 20 30 fref / fc 10 20 30 40 Settling time error (%) 4

th order

3

rd order

2

nd order

10 20 30 fref / fc 5 10 15 20 25 Settling time error (%) 4

th order

3

rd order

2

nd order

10 20 30 fref / fc 10 20 30 Settling time error (%) 4

th order

3

rd order

2

nd order

fz = 0.75fc, τ0 = Tref (wide frequency jump) Higher errors for both models when moving zero from fz = 0.25fc to fz = 0.75fc.

CP-PLL models Design Example

Estimated settling time

z-domain vs. time-domain

10 30 50 70 90 b ≈ c 10 20 30 40 Settling time error %

τ(0)Fref = 1 τ(0)Fref = 0.6 τ(0)Fref = 0.33 τ(0)Fref = 0.25

z-domain for varying τ0, fref ≈ 10fc Error is deeply influenced by first pulse width. For τ0 → 0, error always goes to zero.

10 20 30 fref / fc 5 10 15 20 25 Settling time error (%) 4

th order

3

rd order

2

nd order

10 20 30 fref / fc 10 20 30 Settling time error (%) 4

th order

3

rd order

2

nd order

CP-PLL models Design Example

Outline

1 CP-PLL models The need for accurate PLL models s-domain model z-domain model Time-domain model Comparison between models Phase Noise Models 2 Design Example: Frequency Synthesizer for UWB MB-OFDM UWB communications Synthesizer Architecture PLLs Tuning Range Extension Measured results

CP-PLL models Design Example

s-domain model

CP,n 2π

1 G

2π

FD PFD

• ,n

K

CP

s

LPF VCO Ref

1

C,n N R,n PFD,n

(Fref)

I V

vco

G (s)

θ θ θ θ θ

VCO,n

LF

D,n

Output power spectral density Sθo,n = TR2SθR,n + +TPFD2SθPFD,n + +TCP2SICP,n + +TLF 2SVc,n + +TVCO2SθVCO,n + +TD2SθD,n

CP-PLL models Design Example

s-domain model

CP,n 2π

1 G

2π

FD PFD

• ,n

K

CP

s

LPF VCO Ref

1

C,n N R,n PFD,n

(Fref)

I V

vco

G (s)

θ θ θ θ θ

VCO,n

LF

D,n

Output power spectral density Sθo,n = TR2SθR,n + +TPFD2SθPFD,n + +TCP2SICP,n + +TLF 2SVc,n + +TVCO2SθVCO,n + +TD2SθD,n REF TR = NGc(s) 1 + Gc(s) DIV TD = − NGc(s) 1 + Gc(s) PFD TPFD = 2πG · GLF (s)KVCO s(1 + Gc(s)) CP TCP = 2πGLF (s)KVCO s(1 + Gc(s)) LF TLF = 2πKVCO s(1 + Gc(s)) VCO TVCO = 1 1 + Gc(s)

CP-PLL models Design Example

s-domain model

CP,n 2π

1 G

2π

FD PFD

• ,n

K

CP

s

LPF VCO Ref

1

C,n N R,n PFD,n

(Fref)

I V

vco

G (s)

θ θ θ θ θ

VCO,n

LF

D,n

Output power spectral density Sθo,n = TR2SθR,n + +TPFD2SθPFD,n + +TCP2SICP,n + +TLF 2SVc,n + +TVCO2SθVCO,n + +TD2SθD,n REF TR = NGc(s) 1 + Gc(s) DIV TD = − NGc(s) 1 + Gc(s) PFD TPFD = 2πG · GLF (s)KVCO s(1 + Gc(s)) CP TCP = 2πGLF (s)KVCO s(1 + Gc(s)) LF TLF = 2πKVCO s(1 + Gc(s)) VCO TVCO = 1 1 + Gc(s)

2

N 1 ~fc PNTF log f

Slopes depend on PLL order REF VCO LF

CP-PLL models Design Example

s-domain model

CP,n 2π

1 G

2π

FD PFD

• ,n

K

CP

s

LPF VCO Ref

1

C,n N R,n PFD,n

(Fref)

I V

vco

G (s)

θ θ θ θ θ

VCO,n

LF

D,n

Output power spectral density Sθo,n = TR2SθR,n + +TPFD2SθPFD,n + +TCP2SICP,n + +TLF 2SVc,n + +TVCO2SθVCO,n + +TD2SθD,n REF TR = NGc(s) 1 + Gc(s) DIV TD = − NGc(s) 1 + Gc(s) PFD TPFD = 2πG · GLF (s)KVCO s(1 + Gc(s)) CP TCP = 2πGLF (s)KVCO s(1 + Gc(s)) LF TLF = 2πKVCO s(1 + Gc(s)) VCO TVCO = 1 1 + Gc(s)

VCO REF TOTAL

20log(PNoise) ~fc

VCO noise (and possibly PFD and CP) low freq REF noise plateau

log f

CP-PLL models Design Example

Time-domain model

LOOP VCO DIVIDER FREQ REF

UP

F

DN REF DIV

F F

OUT

DETECTOR FILTER FREQ PHASE PUMP CHARGE

Use time-domain simulator for phase noise analysis Phase noise injected as random jitter which dithers transitions at block outputs. For DIV and REF jitter is added to PFD misalignment. For VCO directly at its output. For the other blocks noise is first converted to jitter at VCO output.

CP-PLL models Design Example

Comparison Examples

2M 10M 100M 20 40

4

th order

s-domain 4

th order

time-domain 2

nd order

s-domain 2

nd order

time-domain

2M 10M 100M

• 20

20 2M 10M 100M

• 40
• 20

20 40 2M 10M 100M

• 20

|θo/θi|

2 Phase Noise Transfer Function (dB)

|θo/θvco|

2 Phase Noise Transfer Function (dB)

fref = 66 MHz fref = 264 MHz fref = 66 MHz fref = 264 MHz

(a) (b) (c) (d)

CP-PLL models Design Example

Comparison Examples

2M 10M 100M 20 40

4

th order

s-domain 4

th order

time-domain 2

nd order

s-domain 2

nd order

time-domain

2M 10M 100M

• 20

20 2M 10M 100M

• 40
• 20

20 40 2M 10M 100M

• 20

|θo/θi|

2 Phase Noise Transfer Function (dB)

|θo/θvco|

2 Phase Noise Transfer Function (dB)

fref = 66 MHz fref = 264 MHz fref = 66 MHz fref = 264 MHz

(a) (b) (c) (d) fref /fc ≈ 5 High amount of

• ut-of-band energy folded
• back. Error taken by

s-domain analysis on integrated phase noise is in the order of 80%.

CP-PLL models Design Example

Comparison Examples

2M 10M 100M 20 40

4

th order

s-domain 4

th order

time-domain 2

nd order

s-domain 2

nd order

time-domain

2M 10M 100M

• 20

20 2M 10M 100M

• 40
• 20

20 40 2M 10M 100M

• 20

|θo/θi|

2 Phase Noise Transfer Function (dB)

|θo/θvco|

2 Phase Noise Transfer Function (dB)

fref = 66 MHz fref = 264 MHz fref = 66 MHz fref = 264 MHz

(a) (b) (c) (d) fref /fc ≈ 5 High amount of

• ut-of-band energy folded
• back. Error taken by

s-domain analysis on integrated phase noise is in the order of 80%. fref /fc ≈ 20 Error taken by s-domain analysis is in the order of 40% (2nd order) and 20% (4th order).

CP-PLL models Design Example

Comparison Examples

2M 10M 100M 20 40

4

th order

s-domain 4

th order

time-domain 2

nd order

s-domain 2

nd order

time-domain

2M 10M 100M

• 20

20 2M 10M 100M

• 40
• 20

20 40 2M 10M 100M

• 20

|θo/θi|

2 Phase Noise Transfer Function (dB)

|θo/θvco|

2 Phase Noise Transfer Function (dB)

fref = 66 MHz fref = 264 MHz fref = 66 MHz fref = 264 MHz

(a) (b) (c) (d)

CP-PLL models Design Example

Results

Models comparison s-domain model can become unreliable if fref/fc < 20. Even z-domain model fails for large frequency jumps.

CP-PLL models Design Example

Results

Models comparison s-domain model can become unreliable if fref/fc < 20. Even z-domain model fails for large frequency jumps. Time-domain model can be used to efficiently simulate wideband PLLs

Fast enough to be extensively used. It can be easily extended to perform averaged analysis of phase noise. Model has been validated designing a frequency synthesizer for UWB MB-OFDM.

CP-PLL models Design Example

Outline

1 CP-PLL models The need for accurate PLL models s-domain model z-domain model Time-domain model Comparison between models Phase Noise Models 2 Design Example: Frequency Synthesizer for UWB MB-OFDM UWB communications Synthesizer Architecture PLLs Tuning Range Extension Measured results

CP-PLL models Design Example

UWB communications

Federal Communication Commission FCC authorizes use of 3.1-to-10.6GHz spectrum. Bandwidth larger than 500MHz. Power spectral density of emission below -41.3 dBm/Hz.

CP-PLL models Design Example

UWB communications

Federal Communication Commission FCC authorizes use of 3.1-to-10.6GHz spectrum. Bandwidth larger than 500MHz. Power spectral density of emission below -41.3 dBm/Hz. Target applications Low range (<10m). High data rates (>100Mb/sec).

CP-PLL models Design Example

UWB communications

10 Mb/s 1 Gb/s 100m 10m 1m 1km 10km 100km b/g n a Bluetooth DATA RATE RANGE WiMAX 802.16 GSM UMTS HSDPA Wi − Fi 802.11 a/b/g/n 802 .15 .3 ZigBee

802.15.14

100 kb/s 100 Mb/s 1 Mb/s 10 kb/s UWB

Target applications Low range (<10m). High data rates (>100Mb/sec).

CP-PLL models Design Example

UWB communications

10 Mb/s 1 Gb/s 100m 10m 1m 1km 10km 100km b/g n a Bluetooth DATA RATE RANGE WiMAX 802.16 GSM UMTS HSDPA Wi − Fi 802.11 a/b/g/n 802 .15 .3 ZigBee

802.15.14

100 kb/s 100 Mb/s 1 Mb/s 10 kb/s UWB

Target applications Low range (<10m). High data rates (>100Mb/sec). Personal Area Networks.

CP-PLL models Design Example

UWB MB-OFDM

WiMedia Alliance Proposal ECMA standards 368 and 369. Data rates up to 480 Mb/sec. QPSK or DCM modulation schemes.

CP-PLL models Design Example

UWB MB-OFDM

WiMedia Alliance Proposal ECMA standards 368 and 369. Data rates up to 480 Mb/sec. QPSK or DCM modulation schemes. ECMA standard 14 bands organized in 6 band groups. MultiBand Orthogonal Frequency Division Multiplexing (MB-OFDM). Different subsets of frequencies allowed outside US.

CP-PLL models Design Example

UWB MB-OFDM

5544 5016 4488 3432 9240 6072 6600 CENTER FREQ EUROPE KOREA JAPAN USA IN MHz GROUP 1 GROUP 2 GROUP 4 GROUP 3 GROUP 5 AVOID DETECT AND AVAILABLE WITH NOT AVAILABLE AVAILABLE 10296 9768 8712 8184 7656 3960 7128

ECMA standard 14 bands organized in 6 band groups. MultiBand Orthogonal Frequency Division Multiplexing (MB-OFDM). Different subsets of frequencies allowed outside US.

CP-PLL models Design Example

UWB MB-OFDM

ECMA standard OFDM symbol last 242.42ns plus 70.08ns for zero-padded suffix. Switching between bands every 312.5ns. 9.5ns of guard interval.

CP-PLL models Design Example

UWB MB-OFDM Transceiver

T/R PA I/Q I/Q LNA VGA OSC LOCAL

CP-PLL models Design Example

Outline

1 CP-PLL models The need for accurate PLL models s-domain model z-domain model Time-domain model Comparison between models Phase Noise Models 2 Design Example: Frequency Synthesizer for UWB MB-OFDM UWB communications Synthesizer Architecture PLLs Tuning Range Extension Measured results

CP-PLL models Design Example

Target Specifications

System specifications Frequency range: 3432-to-10296MHz. 14 center frequencies to be synthesized. Integrated Phase noise below 3.6o

RMS.

Aggregate power of spurs lower than -24dBc. Frequency switching time (for bands in the same group) lower than 9.5ns.

CP-PLL models Design Example

Architecture

Classic solutions Multiple fixed-frequency PLLs not suitable for full spectrum coverage.

CP-PLL models Design Example

Architecture

Classic solutions Multiple fixed-frequency PLLs not suitable for full spectrum coverage. State-of-the-art solutions generally make use of fixed frequency PLLs and extensive mixing.

Area overhead due to the presence of inductors for band-pass filtering. High power consumption.

CP-PLL models Design Example

Architecture

66 MHz PLL WIDEBAND WIDEBAND PLL TREC TREC X TCXO U

IC

M CONTROL

Proposed solution Two PLLs synthesize frequencies in the 6.6-to-10.3GHz range. Two circuits extend the tuning range down to 3.4GHz. MUX switches between the two output every 312.5ns.

CP-PLL models Design Example

Outline

1 CP-PLL models The need for accurate PLL models s-domain model z-domain model Time-domain model Comparison between models Phase Noise Models 2 Design Example: Frequency Synthesizer for UWB MB-OFDM UWB communications Synthesizer Architecture PLLs Tuning Range Extension Measured results

CP-PLL models Design Example

PLL high level design and simulations

Loop design Fourth-order loop. Open-loop unit gain frequency 8MHz. Reference frequency of 66MHz.

/104 −> /156 Gm

Fref

vco

F PFD CP

R D DN UP

LF

CMOS CML2 CML /2 divider /16 −> /132 Dynamic programmable

LC−QVCO FD

ctrl Digital

CP-PLL models Design Example

PLL high level design and simulations

Loop design Fourth-order loop. Open-loop unit gain frequency 8MHz. Reference frequency of 66MHz.

Requires time-domain simulations. Can be derived directly from a crystal oscillator. Allows the use Divide-by-2 CML prescaler.

/104 −> /156 Gm

Fref

vco

F PFD CP

R D DN UP

LF

CMOS CML2 CML /2 divider /16 −> /132 Dynamic programmable

LC−QVCO FD

ctrl Digital

CP-PLL models Design Example

PLL high level design and simulations

Loop design Fourth-order loop. Open-loop unit gain frequency 8MHz. Reference frequency of 66MHz.

Requires time-domain simulations. Can be derived directly from a crystal oscillator. Allows the use Divide-by-2 CML prescaler.

CP current digitally programmable.

/104 −> /156 Gm

Fref

vco

F PFD CP

R D DN UP

LF

CMOS CML2 CML /2 divider /16 −> /132 Dynamic programmable

LC−QVCO FD

ctrl Digital

CP-PLL models Design Example

PLL high level design and simulations

Loop design Fourth-order loop. Open-loop unit gain frequency 8MHz. Reference frequency of 66MHz.

Requires time-domain simulations. Can be derived directly from a crystal oscillator. Allows the use Divide-by-2 CML prescaler.

CP current digitally programmable.

/104 −> /156 Gm

Fref

vco

F PFD CP

R D DN UP

LF

CMOS CML2 CML /2 divider /16 −> /132 Dynamic programmable

LC−QVCO FD

ctrl Digital

Fref 66MHz ICP 200-400µA KVCO ≈600 to 2000MHz/V N 100-156 fc 8MHz fp 30 and 60MHz

CP-PLL models Design Example

Outline

1 CP-PLL models The need for accurate PLL models s-domain model z-domain model Time-domain model Comparison between models Phase Noise Models 2 Design Example: Frequency Synthesizer for UWB MB-OFDM UWB communications Synthesizer Architecture PLLs Tuning Range Extension Measured results

CP-PLL models Design Example

Tuning Range Extension Circuit

vco

F2

1

F

vco

F

DC

F DIVIDER by 2 SSBMs SSBM

• ut

F = X U X U M M

1 1 1

S S

DC

DIV

vco

F

CP-PLL models Design Example

Tuning Range Extension Circuit

vco

F2

1

F

vco

F

DC

F DIVIDER by 2 SSBMs SSBM

• ut

F = X U X U M M

1 1 1

S S

DC

DIV

vco

F

FOUT (MHz) DIV S0S1 FVCO(MHz) F1(MHz) F2(MHz) 3432 2 1 0 6864 6864 3432 3960 2 1 0 7920 7920 3960 4488 2 1 0 8976 8976 4488

CP-PLL models Design Example

Tuning Range Extension Circuit

vco

F2

1

F

vco

F

DC

F DIVIDER by 2 SSBMs SSBM

• ut

F = X U X U M M

1 1 1

S S

DC

DIV

vco

F

FOUT (MHz) DIV S0S1 FVCO(MHz) F1(MHz) F2(MHz) 3432 2 1 0 6864 6864 3432 3960 2 1 0 7920 7920 3960 4488 2 1 0 8976 8976 4488 5016 1.5 0 0 7524 5016 2508 5544 1.5 0 0 8316 5544 2772 6072 1.5 0 0 9108 6072 3036

CP-PLL models Design Example

Tuning Range Extension Circuit

vco

F2

1

F

vco

F

DC

F DIVIDER by 2 SSBMs SSBM

• ut

F = X U X U M M

1 1 1

S S

DC

DIV

vco

F

FOUT (MHz) DIV S0S1 FVCO(MHz) F1(MHz) F2(MHz) 3432 2 1 0 6864 6864 3432 3960 2 1 0 7920 7920 3960 4488 2 1 0 8976 8976 4488 5016 1.5 0 0 7524 5016 2508 5544 1.5 0 0 8316 5544 2772 6072 1.5 0 0 9108 6072 3036 6600-10296 1 X 1 6600-10296

CP-PLL models Design Example

Outline

1 CP-PLL models The need for accurate PLL models s-domain model z-domain model Time-domain model Comparison between models Phase Noise Models 2 Design Example: Frequency Synthesizer for UWB MB-OFDM UWB communications Synthesizer Architecture PLLs Tuning Range Extension Measured results

CP-PLL models Design Example

Test chip

Die TSMC 90nm CMOS process. Die area 2x2mm2. Core area 0.5mm2.

CP-PLL models Design Example

Test chip

Die TSMC 90nm CMOS process. Die area 2x2mm2. Core area 0.5mm2.

QVCOs 85% Loop filters 12% Charge Pumps 1.5% TRECs <1% Dividers <1% PFDs <1%

CP-PLL models Design Example

Output spectra (3.4-9.2GHz range)

Output Spectra of the synthesizer Band 1 (TREC divides by 2).

CP-PLL models Design Example

Output spectra (3.4-9.2GHz range)

Output Spectra of the synthesizer Band 1 (TREC divides by 2). Band 4 (TREC divides by 1.5).

CP-PLL models Design Example

Output spectra (3.4-9.2GHz range)

Output Spectra of the synthesizer Band 1 (TREC divides by 2). Band 4 (TREC divides by 1.5). Band 7 (TREC acts as buffer).

CP-PLL models Design Example

Output spectra (3.4-9.2GHz range)

Output Spectra of the synthesizer Band 1 (TREC divides by 2). Band 4 (TREC divides by 1.5). Band 7 (TREC acts as buffer). Highest spur is at -32dBc.

CP-PLL models Design Example

Output spectra (3.4-9.2GHz range)

Output Spectra of the synthesizer Highest reference spur at -39dBc. Aggregate spur power -27dBc. Specifications require -24dBc.

CP-PLL models Design Example

Phase Noise

Spectrum close-in (1MHz wide). Phase noise -107dBc/Hz at 50KHz. Phase noise -110dBc/Hz at 100KHz. Some spurs due to digital noise.

CP-PLL models Design Example

Phase Noise

Spectrum close-in (1MHz wide). Phase noise -107dBc/Hz at 50KHz. Phase noise -110dBc/Hz at 100KHz. Some spurs due to digital noise. Integrated Phase noise. 1.1o

RMS at 3432MHz.

2.8o

RMS at 9240MHz.

Estimated 3.1o

RMS at 10296MHz.

Specification 3.6o

RMS.

CP-PLL models Design Example

Frequency switching behavior

VCOs control voltages First PLL settles in Ta. Second PLL settles in Tb.

CP-PLL models Design Example

Frequency switching behavior

VCOs control voltages First PLL settles in Ta. Second PLL settles in Tb. Simulated data points are minimum and maximum values for each reference period. Filtering effect due to capacitive load

• n control voltages buffers.

Settling time estimated to be below 300ns.

CP-PLL models Design Example

Results and comparison with previous solutions

[1] [2] [3] This work Technology 180nm CMOS 180nm CMOS 180nm CMOS 90nm CMOS Vsupply 1.8V 1.8V 1.8V 1.2/1.8V Fout 3432-10296 MHz 3432-10296 MHz 6336-8976 MHz 3432-9240 MHz Fref 264MHz 66MHz 528MHz 66MHz Phase

• 98dBc/Hz
• 109.6dBc/Hz
• 99dBc/Hz

noise @1MHz, @1MHz @100KHz Spurs

• 33dBc
• 35dBc
• 52dBc
• 32dBc

Power 117mW 162mW 58mW 55mW Area 2.5x2.2mm2 1.2x1.3mm2 0.7x1.1mm2 0.5mm2 (full chip) (core) (single PLL core) (core)

Comparison Joint power consumption and area occupation are better than state-of-the-art solutions.

1 Che-Fu Liang et al., ISSCC2006. 2 Wei-Zen Chen Tai-You Lu, ISSCC2008. 3 Geum-Young Tak et al., JSSCC2005.