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IIT-Bombay Lecture 32 M. Shojaei Baghini
Module 42 Basic Concepts of 1-bit Pipeline ADC
Reference: Section 17.4 Analog Integrated Circuit Design
- T. C. Caruson, D. A. Johns and K. W. Martin, 2012
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical - - PowerPoint PPT Presentation
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical - - PowerPoint PPT Presentation
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 32: March 26, 2018 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 42 Basic Concepts of 1-bit Pipeline ADC
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IIT-Bombay Lecture 32 M. Shojaei Baghini
Nyquist ADCs (Clock-based Classification)
Source: B. Murmann 2013
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IIT-Bombay Lecture 32 M. Shojaei Baghini
Performance of Data Converters, 2017 Speed, SNDR
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IIT-Bombay Lecture 32 M. Shojaei Baghini
Signal Flow in Pipelined ADC
Ken Martin’s book, 2012 edition
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IIT-Bombay Lecture 32 M. Shojaei Baghini
1-bit Pipelined Converter Stage
Notice: Vref = VFS The expression is simplified based on bi=0 or bi=1. Notice: bi corresponds to the pipelined stage number.
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IIT-Bombay Lecture 32 M. Shojaei Baghini
1-bit Pipelined Converter Stage
Ken Martin’s book, 2012 edition
Quantized equivalent of the ADC
- utput (given to an ideal DAC)
MDAC: Multiplying DAC Notice: Vref = VFS
Notice: bi corresponds to the pipelined stage number.
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IIT-Bombay Lecture 32 M. Shojaei Baghini
Block Diagram of 1-bit Pipelined ADC
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IIT-Bombay Lecture 32 M. Shojaei Baghini