Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: - - PowerPoint PPT Presentation

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Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: - - PowerPoint PPT Presentation

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Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester: Spring 2011 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Date: Jan. 05, 2011 Date: Jan. 05, 2011 Introduction

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Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester: Spring 2011 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in

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IIT-Bombay Lecture 1 M. Shojaei Baghini

Date: Jan. 05, 2011 Date: Jan. 05, 2011

Introduction Introduction

 Prerequisite

 Content of the course  References  CAD Tools and Technology  Learning and Grading  CDEEP-related points  Introduction to the course  Introduction to modern network synthesis

theory

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IIT-Bombay Lecture 1 M. Shojaei Baghini

 Prerequisite: CMOS Analog VLSI

Design (EE618) or Simultaneously

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IIT-Bombay Lecture 1 M. Shojaei Baghini

Content of the Course

 Continuous-time filters (review)

 Discrete-time filters  Basics of Analog to digital converters (ADC)  Basics of Digital to analog converters (DAC)

Parallel ADCs (Flash ADC), Pipelined ADCs

 DACs  Algorithmic ADCs (SAR, ...)

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IIT-Bombay Lecture 1 M. Shojaei Baghini

Content of the Course (cont'd)

 Time Interleaved ADCs

 Oversampled ADCs

  • Mixed-Signal layout
  • Analog and Mixed-Signal IC Test
  • Interconnects
  • Delay locked loops and Phase locked

loops

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IIT-Bombay Lecture 1 M. Shojaei Baghini

References

1) CMOS mixed-signal circuit design by R. Jacob Baker, Wiley India, IEEE press, reprint 2008. 2) Design of analog CMOS integrated circuits by Behzad Razavi, McGraw-Hill, 2003. 3) CMOS circuit design, layout and simulation by

  • R. Jacob Baker, Revised second edition, IEEE

press, 2008. 4) CMOS Integrated ADCs and DACs by Rudy V. de Plassche, Springer, Indian edition, 2005.

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IIT-Bombay Lecture 1 M. Shojaei Baghini

Additional References

5) Electronic Filter Design Handbook by Arthur B. Williams, McGraw-Hill, 1981. 6) Design of analog filters by R. Schauman, Prentice-Hall 1990 (or newer additions) 7) An introduction to mixed-signal IC test and measurement by M. Burns et al., Oxford university press, first Indian edition, 2008. 8) Relevant published papers (will be specified)

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IIT-Bombay Lecture 1 M. Shojaei Baghini

CAD Tools and Technology

  • Mentor Graphics Custom IC Design Flow Tool

Set

  • r Cadence Custom IC Design flow Tool Set
  • Cadence ASIC Design Flow (will be decided)
  • 0.18um UMC CMOS process
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IIT-Bombay Lecture 1 M. Shojaei Baghini

Learning and Grading

  • Course projects/quizzes 30%, Midterm 30% ,
  • Final exam 40%.
  • There is no late submission :)
  • Office hours: Mondays: 12:00pm to 1:pm and

interactions through Moodle

  • Surprise quize!
  • Moodle as the main website for the course

(supported by CDEEP)

  • EE Course website for grading
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IIT-Bombay Lecture 1 M. Shojaei Baghini

CDEEP-Related Points

  • I will repeat your questions.
  • I will write with large font size.
  • You will inform me if camera is switched to PC

while it should show the paper slides and vice versa.

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Contents Contents

  • Properties of driving point

impedance (Zin) in RLC networks

Introduction to Modern Introduction to Modern Network Synthesis Theory Network Synthesis Theory

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Driving Point Impedance (Z Driving Point Impedance (Zin

in)

)

  • f RLC Networks
  • f RLC Networks

An example of RLC network: Lossless 2-port terminated by load resistance R2

IIT-Bombay Lecture 1 M. Shojaei Baghini

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Properties of Z Properties of Zin

in(s) in RLC

(s) in RLC Networks Networks

Z Zin

in(s) is a positive real function.

(s) is a positive real function. Properties of Zin(s) Properties of Zin(s)

  • Zin(s) is a rational function of s.
  • If s is real Zin(s) is also real.
  • Re[s] ≥ 0 ⇒Re[Zin(s)]≥0.

IIT-Bombay Lecture 1 M. Shojaei Baghini

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Properties of Z Properties of Zin

in(s) in RLC

(s) in RLC Networks Networks (cont'd)

(cont'd)

  • For Zin(s) order of the numerator polynomial

differs from order of the denominator polynomial at most by unity.

  • For a positive real Zin(s), poles and zeros of

Zin(s) are placed on or on the left side of “jω” axis. Imaginary poles are simple with positive real residues. Further Re [Zin(jω)] ≥0 for all values of ω.

IIT-Bombay Lecture 1 M. Shojaei Baghini

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Properties of Z Properties of Zin

in(s) in RLC

(s) in RLC Networks - Example Networks - Example

  • Zin(s) is a rational function of s.
  • Order of denominator = 3
  • Order of numerator = 4
  • Poles with negative or zero real part

IIT-Bombay Lecture 1 M. Shojaei Baghini

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Basic Concepts Basic Concepts

  • Dynamic range
  • Phase Delay
  • Group Delay
  • Minimum Phase TF

IIT-Bombay Lecture 1 M. Shojaei Baghini

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End of Lecture 1