Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: - - PowerPoint PPT Presentation

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Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: - - PowerPoint PPT Presentation

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Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester: Spring 2011 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Date: March 04, 2011 Date: March 04, 2011 Nyquist-Rate

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Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester: Spring 2011 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in

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IIT-Bombay Lecture 13 M. Shojaei Baghini

Date: March 04, 2011 Date: March 04, 2011

Nyquist-Rate ADCs -

Nyquist-Rate ADCs - High-Speed Architectures - High-Speed Architectures - Flash and subranging ADC Flash and subranging ADC

Contents Contents

 Architecture of Flash ADC  Performance and effect of nonidealities  Example  Subranging ADC

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IIT-Bombay Lecture 13 M. Shojaei Baghini

Fastest ADC – Flash ADC

 Fastest conversion rate  No need to S&H if dynamic

comparators are used.

 2N-1 comparators  Dynamic Power Dissipation  Variabilities across comparators

and resistors

 Heavy loading of input and clock

drivers

 Sensitivity to skew between

comparator clocks

 Offset compensation methods

(at input or output of comparator)

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IIT-Bombay Lecture 13 M. Shojaei Baghini

Effect of mismatches and process variations Example Example N = 6 bits , VFS=1.2V Maximum|∆R/R| for two adjacent resistors = 1% Reference point for resistor variation: Center of resistive ladder. Objectives

  • DNL and INL values corresponding to every code.
  • Maximum acceptable Vos,in of comparators

Details are given in lecture notes. Students will draw the nonlinearity plots.

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IIT-Bombay Lecture 13 M. Shojaei Baghini

Two-Step or Subranging ADC

Gain = 2N/2

 No. of Comparators = 2(2N/2-1) + DAC comparator

and compared to flash ADC

 Relaxed resolution at the input of comparators  More latency but similar throughput

All components should be at least 8-bit accurate!

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IIT-Bombay Lecture 13 M. Shojaei Baghini

  • Reference for Switched Capacitor Filter

simulation from VLSI lab Wiki page

  • FFT concept and simulation in Matlab
  • Design techniques for HS Comparator

design, B. Razavi, JSSC, 1992 Warm up exercises for the next course project

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IIT-Bombay Lecture 13 M. Shojaei Baghini

End of lecture 13