mixed signal vlsi design course code ee719 ee410
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Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester: Spring 2011 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Date: March 04, 2011 Date: March 04, 2011 Nyquist-Rate


  1. Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester: Spring 2011 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1

  2. 2 2 Date: March 04, 2011 Date: March 04, 2011 Nyquist-Rate ADCs - Nyquist-Rate ADCs - High-Speed Architectures - High-Speed Architectures - Flash and subranging ADC Flash and subranging ADC Contents Contents  Architecture of Flash ADC  Performance and effect of nonidealities  Example  Subranging ADC IIT-Bombay Lecture 13 M. Shojaei Baghini

  3. 3 3 Fastest ADC – Flash ADC  Fastest conversion rate  No need to S&H if dynamic comparators are used.  2 N -1 comparators  Dynamic Power Dissipation  Variabilities across comparators and resistors  Heavy loading of input and clock drivers  Sensitivity to skew between comparator clocks  Offset compensation methods (at input or output of comparator) IIT-Bombay Lecture 13 M. Shojaei Baghini

  4. 4 4 Effect of mismatches and process variations Example Example N = 6 bits , V FS =1.2V Maximum| ∆ R/R| for two adjacent resistors = 1% Reference point for resistor variation: Center of resistive ladder . Objectives - DNL and INL values corresponding to every code . - Maximum acceptable V os,in of comparators Details are given in lecture notes. Students will draw the nonlinearity plots. IIT-Bombay Lecture 13 M. Shojaei Baghini

  5. 5 5 Two-Step or Subranging ADC Gain = 2 N/2 All components should be at least 8-bit accurate!  No. of Comparators = 2(2 N/2 -1) + DAC comparator and compared to flash ADC  Relaxed resolution at the input of comparators  More latency but similar throughput IIT-Bombay Lecture 13 M. Shojaei Baghini

  6. 6 6 Warm up exercises for the next course project - Reference for Switched Capacitor Filter simulation from VLSI lab Wiki page - FFT concept and simulation in Matlab - Design techniques for HS Comparator design, B. Razavi, JSSC, 1992 IIT-Bombay Lecture 13 M. Shojaei Baghini

  7. 7 7 End of lecture 13 IIT-Bombay Lecture 13 M. Shojaei Baghini

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