Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical - - PowerPoint PPT Presentation

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Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical - - PowerPoint PPT Presentation

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Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 26: March 12, 2018 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 34 Introduction to Successive Approximation

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Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 26: March 12, 2018

Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in

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IIT-Bombay Lecture 26 M. Shojaei Baghini

Module 34 Introduction to Successive Approximation Register (SAR) ADC

Reference: Section 17.2 Analog Integrated Circuit Design

  • T. C. Caruson, D. A. Johns and K. W. Martin, 2012
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IIT-Bombay Lecture 26 M. Shojaei Baghini

Nyquist ADCs (Clock-based Classification)

Source: B. Murmann 2013

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Performance of Data Converters, 2017 Power, Speed, SNDR

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  • SAR-based

Interleaving

  • SAR-based

pipelining

  • CT delta-

sigma with pipelining Source: ISSCC 2017

IIT-Bombay Lecture 26 M. Shojaei Baghini

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Performance of Data Converters, 2017 Signal BW and SNDR

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  • SAR-based

Interleaving

  • SAR-based

pipelining

  • CT delta-

sigma with pipelining Source: ISSCC 2017

IIT-Bombay Lecture 26 M. Shojaei Baghini

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Successive Approximation Register ADC – Binary Search

Source: Tutorial 1080, Understanding SAR ADCs, Maxim Integrated, 2010

IIT-Bombay Lecture 26 M. Shojaei Baghini

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Charge Redistribution SAR ADC

  • Bit by bit charge redistribution (or charge scaling) A-to-D

conversion

Ken Martin’s book, 2012 edition

  • Sharing capacitors for T&H, charge scaling DAC and

establishing Vin – Vout,DAC Small signal analysis

IIT-Bombay Lecture 26 M. Shojaei Baghini

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Successive Approximation Register ADC (Hold

mode, Establishing the first component of subtraction)

Ken Martin’s book, 2012 edition

Small signal analysis

IIT-Bombay Lecture 26 M. Shojaei Baghini

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Successive Approximation Register ADC (Subtraction)

Ken Martin’s book, 2012 edition

Small signal analysis

IIT-Bombay Lecture 26 M. Shojaei Baghini

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Factors Affecting Speed and Accuracy in SAR ADC

  • Slow (bit at a time)
  • Delay of each conversion cycle - Settling time of

the DAC, delay of the comparator and control logic delay (it’s a simple logic)

  • Comparator resolution
  • Comparator offset contributes to the ADC offset.
  • DAC nonlinearity is the main factor in determining

the SAR ADC nonlinearity.

  • DAC and comparator noise contribute to the ADC

noise.

  • Buffering

IIT-Bombay Lecture 26 M. Shojaei Baghini

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IIT-Bombay Lecture 26 M. Shojaei Baghini

End of Lecture 26